Package Substrate Pin Layout for Signal Isolation With Fewer Pins

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Solution Overview

Problem

The existing design of high-speed single-ended signal pins in chip packaging results in a large number of pins and significant signal crosstalk due to the absence of reference ground pins, leading to increased area occupation and reduced signal integrity.

Innovation Solution

A pin arrangement structure with alternating first and second pin units, staggered in one direction, and incorporating reference ground pins to isolate high-speed single-ended signal pins, along with separate regions for high-speed differential and low-speed signal pins, reducing the overall pin count and crosstalk.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high-speed single-ended signal pins are arranged in an array with reference ground pins for each signal pin, then signal isolation is improved, but the number of pins increases and occupied area increases

Engineering Contradiction:

Improvesignal isolationVSAvoidnumber of pins

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

Multiple reference ground pins are merged to jointly surround a single third pin unit containing high-speed differential signal pins. This consolidation approach reduces the total number of reference ground pins needed compared to providing dedicated reference ground pins for each signal pin, while still maintaining effective signal isolation and reducing crosstalk.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Reference ground pins are designed to serve multiple functions: they surround third pin units containing high-speed differential signal pins, provide isolation for multiple signal types (both single-ended and differential signals), and reduce overall pin count. This multi-functional design optimizes the use of reference ground pins across different signal arrangements.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Quantity of substance

If high-speed single-ended signal pins are arranged in close proximity without reference ground pin isolation, then the number of pins is reduced, but signal crosstalk increases

Engineering Contradiction:

Improvenumber of pinsVSAvoidsignal crosstalk

Core Design Contradiction:

Quantity of substanceVSObject-generated harmful factors

Solution Approach 1:

Reference ground pins are introduced as intermediary elements between high-speed single-ended signal pins and high-speed differential signal pins. These reference ground pins act as mediators that provide electrical isolation and reduce crosstalk between adjacent signal pins, enabling closer spacing while maintaining signal integrity.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

Reference ground pins are strategically positioned at specific locations where crosstalk is most problematic - surrounding third pin units and interspersed among first and second pin units. This localized placement of reference ground pins provides targeted isolation where needed most, rather than uniformly distributing all reference ground pins throughout the entire array.

Inventive Principle:

Principle #3Local quality

3Reliability

If more reference ground pins are added to isolate high-speed single-ended signal pins, then signal quality is improved, but device complexity increases

Engineering Contradiction:

Improvesignal qualityVSAvoidpin arrangement complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Reference ground pins are merged to jointly surround multiple third pin units containing high-speed differential signal pins. This consolidation reduces the total number of reference ground pins needed compared to providing individual reference ground pins for each signal pin, while still maintaining effective signal isolation and reducing crosstalk.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260032807A1Pin arrangement structure, package substrate, and package structure

Publication Date: 2026.01.29 GLENFLY TECH CO LTD

AI summary

The present disclosure relates to a pin arrangement structure, a package substrate, and a package structure, and relates to the field of package technologies. The pin arrangement structure includes a first pin array region. First pin units and second pin units in the first pin array region are sequentially arranged alternately in a first direction, and the first pin units and the second pin units are both provided with high-speed single-ended signal pins. A number of pins of the first pin units in a second direction is greater than a number of pins of the second pin units in the second direction, two adjacent second pin units are staggered in the first direction, and first reference ground pins are arranged at other pin positions of the first pin array region. Therefore, isolation is formed between the high-speed single-ended signal pins, improving isolation between signals and reducing crosstalk between the signals. At the same time, compared with existing arrangement, the arrangement reduces the number of pins and saves a region area of the pins.