Package Structure Reducing Thickness via Planar Wire Routing
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Solution Overview
Problem
Conventional wire bonding techniques for chip packaging result in increased package thickness due to wire loops, making it difficult to meet low-profile requirements in modern electronic equipment.
Innovation Solution
A package structure design where the substrate is disposed on the chip with a first solder mask and core layer, exposing bonding pads, and wires are connected between the patterned circuit layers and bonding pads, allowing the molding compound to be coplanar with the substrate surface, thus reducing overall thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding technology is used to electrically connect chip to substrate, then electrical connection is achieved, but package thickness increases due to wire loops
Solution Approach 1:
The patent transitions from traditional wire bonding (requiring vertical wire loops) to a planar routing approach where connection paths are extended along the substrate surface. By utilizing the lateral dimension of the substrate rather than vertical wire loops, the connection is achieved without increasing package thickness, effectively resolving the contradiction between reliable electrical connection and low profile requirement
2Reliability
If wires are extended upward and then moved downward for stitching, then electrical connection is established, but loop height increases package thickness
Solution Approach 1:
The patent extracts the wire loop configuration from the traditional wire bonding process. Instead of forming vertical loops that extend upward and downward, the wires are routed horizontally along the substrate surface, eliminating the vertical loop height component that contributes to package thickness while maintaining electrical connectivity
3Ease of manufacture
If chip is disposed on substrate at higher level, then wire bonding is enabled, but low-profile requirements cannot be met
Solution Approach 1:
The patent inverts the traditional approach by placing the substrate on the chip rather than the chip on the substrate. This inversion allows the substrate to serve as the bonding platform, with wires routed along its surface, thereby achieving wire bonding functionality without the need for elevated chip positioning that increases package thickness
Data Source
AI summary
A package structure includes a chip, a substrate, wires and a molding compound. The chip includes an active surface, a back surface and bonding pads disposed on the active surface. The substrate includes first and second solder masks, first and second patterned circuit layers and a core layer having a first surface and a second surface. The first patterned circuit layer is disposed on the first solder mask. The core layer disposed on the first solder mask with the first surface partially exposes the first patterned circuit layer. The substrate disposed on the active surface with the first solder mask exposes the bonding pads. The second patterned circuit layer disposed on the second surface. The second solder mask partially covers the second patterned circuit layer. The wires are connected between the first patterned circuit layer and the bonding pads. The molding compound covers the chip, the wire and the substrate.