Semiconductor Package Planarization for 3D Die Interconnect and Cooling
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Solution Overview
Problem
As high-performance computing (HPC) packages grow in size, communication between semiconductor dies becomes increasingly challenging, requiring innovative packaging solutions to enhance data transfer rates and reduce latency.
Innovation Solution
The proposed semiconductor package structure includes a first logic die surrounded by second logic dies, with a redistribution layer and conductive features for electrical connectivity. Additionally, memory dies and heat conduction blocks are integrated in a layered configuration, with encapsulants and thermally conductive adhesives used to facilitate heat dissipation and electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package size is increased to accommodate HPC components, then more dies can be integrated, but communication between dies becomes more challenging
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of dies to a three-dimensional stacked configuration. Multiple logic dies are vertically stacked and interconnected through through-silicon vias (TSVs), enabling high-performance computing functionality while maintaining compact footprint and improving communication efficiency between dies through vertical interconnects.
Solution Approach 2:
The patent implements a nested structure where memory dies are stacked above logic dies, and multiple functional layers are integrated vertically. The through-silicon vias penetrate through multiple die layers, creating a nested interconnection scheme where signal paths are embedded within the stacked die structure, enabling efficient communication despite the increased number of integrated components.
2Quantity of substance
If more dies are integrated in the package, then computing performance increases, but heat dissipation becomes more difficult
Solution Approach 1:
The patent introduces an intermediate heat dissipation structure consisting of heat sinks and thermal interface materials positioned between the stacked dies and the external environment. These intermediary thermal management components facilitate heat transfer from the high-density die stack to the surrounding air or cooling systems, enabling effective temperature control in multi-die HPC packages.
3Speed
If complex interconnect structures are used to improve communication, then data transfer rates increase, but manufacturing complexity increases
Solution Approach 1:
The patent replaces complex mechanical routing and wiring approaches with a standardized semiconductor fabrication process using through-silicon vias and redistribution layers. The interconnect structure is formed through sequential deposition, etching, and planarization steps that are integrated into the existing CMOS manufacturing flow, enabling high-speed communication without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This packaging solution improves communication between dies by enhancing electrical connectivity and heat dissipation, thereby supporting high data transfer rates and reducing latency in HPC applications.
Implementation Method 1
thermally conductive adhesives used to facilitate heat dissipation
Data Source
AI summary
A method of forming a semiconductor package includes the following steps. A first die and at least one silicon block are provided, wherein the at least one silicon block has an adhesive on a first surface. A first encapsulating material is formed, to encapsulate the first die and the at least one silicon block. A planarization process is performed on the first encapsulating material, wherein a second surface opposite to the first surface of the at least one silicon block is coplanar with a top surface of the first encapsulant.