Package Structure With Polymer Layers Preventing Die Shift
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Solution Overview
Problem
Conventional IC package structures face alignment failures due to insufficient adhesion between semiconductor dies and carriers during high-pressure molding, leading to shifts and fabrication cost issues in achieving high-density, miniature designs for modern electronic devices.
Innovation Solution
A package structure comprising multiple polymer layers, high-filler dielectric layers, and conductive passages is developed, where a first polymer layer with a larger surface area supports a second polymer layer with identical surface area, and high-filler dielectric layers enclose conductive wiring to securely position semiconductor chips, preventing shifts during molding. The fabrication method involves forming these layers and passages to ensure strong adhesion and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a removable sticky substance is used to adhere the semiconductor die to the carrier wafer, then the adhesion is initially sufficient for placement, but the adhesion strength is insufficient during the high-pressure molding process causing the semiconductor die to shift
Solution Approach 1:
The patent applies a first polymer layer to the carrier wafer before placing the semiconductor die, and then applies a second polymer layer to the die before bonding. This preliminary preparation of adhesive layers ensures sufficient adhesion strength is established before the molding process begins, preventing die shift during high-pressure molding while maintaining alignment precision.
2Reliability
If conventional packaging methods are used, then the process is simpler, but alignment failures occur due to die shifting during molding
Solution Approach 1:
The patent employs a composite adhesive structure consisting of two different polymer layers with distinct properties. The first polymer layer provides initial adhesion to the carrier, while the second polymer layer provides enhanced adhesion to the die and resistance to molding pressure. This composite approach improves alignment reliability without requiring fundamentally new packaging methods, thus limiting the increase in device complexity.
3Productivity
If high-pressure molding is applied to achieve high-density packaging, then more components can be integrated, but the semiconductor die may shift position if adhesion is insufficient
Solution Approach 1:
The patent changes the adhesive parameters by using two polymer layers with different adhesive properties rather than a single sticky substance. This parameter change allows the system to withstand high-pressure molding forces while maintaining die position precision, enabling high-density integration without sacrificing manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents semiconductor die shifts during molding, ensuring accurate circuitry alignment and reducing fabrication costs by enhancing adhesion and stability within the package structure, thereby supporting high-density and miniature IC designs.
Implementation Method 1
a first polymer layer with a first surface; a second polymer layer with a second surface on the first polymer layer... the second polymer layer to be adhered to the first polymer layer
Data Source
AI summary
A package structure is provided, which includes: a first polymer layer with a first surface; a second polymer layer with a second surface on the first polymer layer; a circuit device with opposing third and fourth surfaces, the circuit device disposed on the second polymer layer and with multiple metal pads on the fourth surface; a first high-filler dielectric layer enclosing the circuit device and the second polymer layer and covering the first polymer layer; a first conductive wiring formed on the first high-filler dielectric layer; a first conductive passage formed in the first high-filler dielectric layer and connecting the first conductive wiring to the metal pads; a second high-filler dielectric layer enclosing the first conductive wiring and covering the first high-filler dielectric layer; and a second conductive passage formed in the second high-filler dielectric layer and connecting the first conductive wiring to an external circuit.