Electronic Package Redistribution Layer Line Width Matching
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Solution Overview
Problem
Conventional semiconductor packaging faces challenges in miniaturization due to mismatched line spacing and width between semiconductor chips and package substrates, leading to reduced process yield and increased production costs as the number of circuit layers increases.
Innovation Solution
The proposed solution involves a circuit structure with a redistribution layer and multiple organic material substrates stacked via supporting bodies, where the line width or spacing of the redistribution layer matches the electronic element, and the coefficient of thermal expansion of the substrates is tailored to improve thermal management and yield control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size specification of the semiconductor chip is miniaturized, then the integration density is improved, but the line spacing/line width of the integrated circuit is reduced, making it difficult to match with conventional ABF type package substrates
Solution Approach 1:
The package substrate is divided into multiple layers (first organic material substrate layer, second organic material substrate layer, third organic material substrate layer) with different line widths and spacings. Each layer is designed with specific line dimensions to progressively transition from finer pitch near the chip to coarser pitch at the package edges, enabling matching between miniaturized chip circuits and package substrate routing.
2Adaptability or versatility
If the package substrate size is increased to accommodate more functional requirements, then the functional capacity is improved, but the number of circuit layers increases, reducing process yield
Solution Approach 1:
Different regions of the package substrate are designed with different numbers of circuit layers and different line dimensions. Areas requiring high functionality have more layers and denser routing, while peripheral areas have fewer layers and coarser routing. This localized optimization maintains necessary functional capacity while reducing overall process complexity and improving yield.
3Adaptability or versatility
If the number of circuit layers is increased to meet functional requirements, then the functionality is improved, but the production cost and production time increase rapidly
Solution Approach 1:
The circuit layers are segmented into multiple organic material substrate layers, each with a specific number of layers and line dimensions optimized for its functional region. This allows the package to achieve high functionality in critical areas without uniformly increasing the layer count across the entire substrate, thereby controlling production time and cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective miniaturized packaging by matching line widths and spacings, improving process yield and reducing manufacturing costs and time, while ensuring reliable thermal expansion management.
Implementation Method 1
a first organic material substrate disposed on the second surface of the circuit structure and having a first circuit layer; and at least one second organic material substrate having a second circuit layer, wherein the first organic material substrate is stacked on the at least one second organic material substrate via a plurality of supporting bodies
Implementation Method 2
the redistribution layer is electrically connected to the second circuit layer via the first circuit layer
Implementation Method 3
a coefficient of thermal expansion of the at least one second organic material substrate is greater than a coefficient of thermal expansion of the circuit structure and a coefficient of thermal expansion of the first organic material substrate
Data Source
AI summary
An electronic package is provided, in which a circuit structure is disposed on the uppermost side of a plurality of stacked organic material substrates for connecting an electronic element, so that a line width/line spacing of a redistribution layer of the circuit structure conforms with a line width/line spacing of the electronic element. Therefore, when the size specification of the electronic element is designed to be miniaturized, the redistribution layer configured in the circuit structure can effectively match the line spacing/line width of the electronic element, so as to meet the requirements of miniaturized packaging.