Semiconductor Package Redistribution Plating Without Additive Voids
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Solution Overview
Problem
Existing semiconductor manufacturing processes face inefficiencies in forming redistribution layers due to the use of electrolytic plating with additives, leading to impurities, void formation, and reduced mechanical strength, which affects production costs and device performance.
Innovation Solution
A semiconductor package manufacturing process that utilizes a plating process with a current density of 4-6 amperes per square decimeter to form redistribution circuit layers without additives, resulting in improved mechanical strength, reduced impurities, and enhanced production efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If electrolytic plating with additives is used to form redistribution layers, then coating performance is improved, but impurities and voids are introduced reducing mechanical strength
Solution Approach 1:
The patent removes harmful additives (suppressors, promoters, brighteners) from the electrolytic plating solution, extracting only the essential copper sulfate and water components. This extraction eliminates the source of impurities and voids while maintaining the core plating function, directly resolving the contradiction between coating performance and mechanical strength.
Solution Approach 2:
The patent changes the chemical composition parameters of the plating solution by eliminating additive components and controlling copper sulfate concentration. This parameter change transforms the plating process from one that produces strong coatings with impurities to one that produces both strong coatings and high mechanical strength through a simplified chemistry.
2Ease of manufacture
If conventional electrolytic plating processes are used, then redistribution layers are formed, but production efficiency is limited and costs increase
Solution Approach 1:
The patent extracts and removes complex additive systems from the plating process, simplifying the manufacturing procedure. This removal of unnecessary chemical complexity reduces process steps, minimizes quality control burden, and eliminates the need for managing multiple chemical suppliers, thereby improving production efficiency while maintaining ease of manufacture.
Solution Approach 2:
Instead of adding numerous additives to achieve desired plating properties, the patent inverts the approach by using a minimal component system (copper sulfate and water only) and achieving superior results through parameter optimization and process control, thereby simplifying manufacturing and boosting productivity.
3Manufacturing precision
If additives are used in plating solution, then coating properties are enhanced, but impurities accumulate reducing signal integrity
Solution Approach 1:
The patent extracts and eliminates organic additives from the plating solution, removing the source of impurity introduction. This extraction ensures that copper deposition occurs without contaminating the redistribution layer with organic residues that would compromise signal integrity, while still achieving enhanced coating properties through controlled electrolysis.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process increases production efficiency by three times, reduces production costs by 1%, and enhances mechanical strength and signal integrity while minimizing voids and delamination risks in the redistribution structure.
Implementation Method 1
a plating process carried out at a current density of substantially from 4-6 amperes per square decimeter (ASD)
Data Source
AI summary
A semiconductor package includes a semiconductor die, an insulating encapsulation, and a redistribution circuitry. The semiconductor die includes a substrate, an electrical terminal disposed over a front side of the substrate, and an insulation layer disposed over the front side of the substrate and laterally covering the electrical terminal. The insulating encapsulation extends along sidewalls of the substrate and the insulation layer of the semiconductor die. The redistribution circuitry is disposed on the insulating encapsulation, the insulation layer of the semiconductor die, and the electrical terminal of the semiconductor die. The redistribution circuitry includes a circuit portion and a first via portion connected to the circuit portion and the electrical terminal, and the first via portion is concaved toward the electrical terminal.