Semiconductor Package Reinforcement for Heat Sink Crack Resistance

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Solution Overview

Problem

The rigidity or stiffness of semiconductor package structures is relatively low, leading to potential cracks that can damage the circuit portion and reduce yield due to the transmission of pressing forces from attached heat sinks.

Innovation Solution

Incorporating a reinforcement structure above the interconnection portions of the circuit layer, which includes a dielectric layer and circuit layers, to enhance the rigidity and prevent crack propagation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If a heat sink is attached to the semiconductor package structure to dissipate heat, then heat dissipation performance is improved, but pressing force is transmitted to the package structure causing cracks and reducing reliability

Engineering Contradiction:
Improveheat dissipation performanceVSAvoidcrack resistance
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent introduces a reinforcement structure as an intermediary element between the heat sink and the semiconductor package structure. This reinforcement structure absorbs and distributes the pressing force from the heat sink, preventing direct transmission to the package structure and avoiding crack formation while maintaining heat dissipation functionality

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The reinforcement structure is formed using a composite material system comprising a first material layer and a second material layer with different mechanical properties. The first material layer provides flexibility to absorb pressing force, while the second material layer provides structural support, creating a composite structure that resolves the contradiction between heat dissipation and crack resistance

Inventive Principle:
Principle #40Composite materials

2Ease of manufacture

If the semiconductor package structure is made with standard materials, then manufacturing cost is reduced, but rigidity is insufficient leading to crack formation under pressing force

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidrigidity
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The patent employs a composite material structure consisting of a first material layer and a second material layer with distinct mechanical characteristics. This composite approach enhances the overall rigidity and strength of the package structure to resist cracking under pressing force, while the materials selected are compatible with standard semiconductor manufacturing processes

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The reinforcement structure is formed in advance during the manufacturing process, before the package structure is subjected to operational pressing forces. This preliminary strengthening action ensures the package structure has adequate rigidity from the outset to prevent crack formation

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250210544A1Package structure, assembly structure and method for manufacturing the same
Publication Date: 2025.06.26 ADVANCED SEMICON ENG INC
  • US20250210544A1 patent drawing
  • US20250210544A1 patent drawing
  • US20250210544A1 patent drawing

AI summary

A package structure includes a wiring structure, a first electronic device, a second electronic device and a reinforcement structure. The wiring structure includes at least one dielectric layer, and at least one circuit layer in contact with the dielectric layer. The at least one circuit layer includes at least one interconnection portion. The first electronic device and the second electronic device are electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the at least one interconnection portion of the at least one circuit layer. The reinforcement structure is disposed above the at least one interconnection portion of the at least one circuit layer.