3D IC Package with Ring Frame TSVs for Tamper Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional 3D IC integration technologies face challenges in reducing package footprint, maintaining thermal stability, and providing security features, particularly in achieving a compact and secure internal volume for multilayer circuit packages.
Innovation Solution
The implementation of a microelectronic packaging structure that includes a base substrate, a lid substrate, and a ring frame with through silicon vias (TSVs) to create a protected volume, which incorporates conductive pillars and edge caps for impedance-based tamper detection and thermal management, utilizing anisotropic adhesive and conductive materials for enhanced security and thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional 3D IC integration is used with multiple wafers interconnected by TSVs, then circuit speed and storage bandwidth are improved, but package footprint and security protection are compromised
Solution Approach 1:
The patent transitions from conventional planar 2D packaging to a vertical 3D stacked architecture. Multiple substrate levels are stacked vertically with TSVs providing inter-layer interconnect, enabling compact footprint while maintaining high-speed performance through shortened interconnect lengths in the vertical dimension.
Solution Approach 2:
The patent implements nested structures where ring frames with TSVs are embedded within substrate levels, and multiple substrate levels are stacked within a compact package volume. This nesting enables dense integration of interconnect structures within the limited package space.
2Quantity of substance
If silicon layer is thinned and TSV size is scaled for higher density, then integration density is improved, but structural robustness and thermal stability deteriorate
Solution Approach 1:
The patent employs composite material structures including metal-filled TSVs within thinned silicon layers, and ring frames comprising multiple materials (e.g., metal, ceramic, or polymer composites) to provide both high integration density and enhanced structural robustness. The composite construction allows thin silicon layers to maintain strength through reinforced TSV structures.
Solution Approach 2:
The patent incorporates protective ring frames with TSVs before final assembly to cushion and protect the thinned silicon layers during handling and operation. These pre-installed protective structures prevent mechanical damage while enabling high-density integration.
3Ease of manufacture
If conventional packaging structures are used, then manufacturing simplicity is maintained, but security features and protected internal volume are insufficient
Solution Approach 1:
The patent designs ring frames with TSVs that serve multiple functions: providing electrical interconnect between layers, forming protective barriers for security, and creating defined protected volumes. This multi-functionality achieves enhanced security without significantly complicating the manufacturing process, as the same TSV fabrication steps serve both interconnect and security purposes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the package footprint, maintains thermal stability, and provides robust security features by enabling tamper detection and efficient thermal management through impedance fingerprinting and conductive mesh structures, ensuring the integrity of the package.
Implementation Method 1
a system comprises Si, Cu, and solder for thermal performance and structural robustness
Implementation Method 2
electronic capacitive, resistive, and/or impedance-based sensor circuitry in the protected volume
Data Source
AI summary
Methods and apparatus for providing an assembly including a base substrate, a lid substrate, and a ring frame between the base substrate and the lid substrate to define a protected volume, where the ring frame includes through vias. A die may be contained in the protected volume. Sensor circuitry can include conductive pillars in the protected volume and the die can include circuity to determine an impedance of the pad and the pillars for tamper detection. An edge cap can be coupled to at least one side of the assembly for tamper detection.