Semiconductor Package Surface Roughness for Flux Containment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor packaging lies in effectively managing the flow and concentration of flux during the assembly process, which can lead to delamination issues due to uneven surface roughness, particularly when passive elements are mounted on package substrates using solder paste.
Innovation Solution
The semiconductor package design includes specific surface roughness patterns in the passive element adjacent regions and remaining regions, with varying roughness levels to control flux flow and concentration, thereby reducing the risk of delamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the package substrate has a uniform surface roughness, then the manufacturing process is simple, but flux flows uncontrollably causing delamination and contamination
Solution Approach 1:
The patent applies local quality by creating different surface roughness characteristics in different regions of the package substrate. Specifically, the passive element adjacent region has a first surface roughness while the remaining region has a second surface roughness that is different from the first. This localized variation in surface properties allows flux to be contained in specific areas, preventing unwanted flow and contamination while maintaining overall manufacturing feasibility.
2Productivity
If solder paste is used to mount passive elements, then the mounting process is efficient, but flux contamination and delamination occur due to uncontrolled flux flow
Solution Approach 1:
The patent uses local quality principles by modifying the surface roughness specifically in the passive element adjacent region to contain flux during the solder paste mounting process. The first surface roughness in this region prevents flux from flowing into the remaining region, thereby eliminating contamination while preserving the efficiency of the solder paste mounting process.
Solution Approach 2:
The patent converts the potentially harmful flux flow into a beneficial contained feature by using surface roughness variations to direct and limit flux movement. The flux that would normally cause contamination is instead channeled and contained within the passive element adjacent region, where it serves its intended function without causing harm.
3Reliability
If the surface roughness is increased to control flux, then flux flow is restricted, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by implementing surface roughness modifications only in specific regions (passive element adjacent region with first surface roughness and remaining region with second surface roughness) rather than uniformly across the entire substrate. This localized approach prevents delamination while minimizing the overall manufacturing complexity compared to treating the entire surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively manages flux distribution, preventing contamination of bump pads and delamination by ensuring controlled flux flow, thus enhancing the reliability and integrity of the semiconductor package.
Implementation Method 1
the passive element adjacent region includes a first sub-region on a first side of the first passive element, a second sub-region on a second side opposite the first side of the first passive element, a third sub-region on a third side of the first passive element, and a fourth sub-region on a fourth side opposite the third side of the first passive element, and a roughness of an upper surface of at least one of the first sub-region to the fourth sub-region is greater than the roughness of an upper surface of the remaining region
Data Source
AI summary
A semiconductor package includes a substrate having a passive element region, a peripheral region adjacent to the passive element region, and a remaining region, a first passive element on an upper surface of the passive element region, a first semiconductor chip on an upper surface of the remaining region, and a sealing portion covering the substrate, the first passive element, and the first semiconductor chip, wherein the peripheral region includes a first sub-region on a first side of the first passive element, a second sub-region on a second side opposite the first side, a third sub-region on a third side of the first passive element, and a fourth sub-region on a fourth side opposite the third side, and wherein a roughness of an upper surface of at least one of the first to fourth sub-regions is greater than a roughness of the upper surface of the remaining region.