Semiconductor Package Routing Layout for Crosstalk and Clock Skew
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges such as clock skew, crosstalk, and increased costs due to the need for multiple metallization layers in high-speed chip-to-chip communication, particularly in 2.5D and 3D semiconductor packages.
Innovation Solution
The solution involves same-level electrical routing between chips without additional vias, inserting ground/power lines between signal lines to provide a current return path and reduce crosstalk, and optimizing metal line configurations with acute-angle or right-angle turns to maintain communication efficiency while minimizing metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple metallization layers are used for high-speed chip-to-chip communication, then communication reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent transitions from vertical stacking of multiple metal layers to a lateral routing approach where a single metal layer is extended and routed around underlying structures (such as through-silicon vias or contact holes) to achieve high-speed signal transmission. This dimensional change from vertical to lateral routing reduces the number of metal layers needed while maintaining communication reliability.
2Area of stationary object
If signal lines are routed closely together to increase density, then area is reduced, but crosstalk between adjacent signal lines increases
Solution Approach 1:
The patent introduces ground lines as intermediary structures positioned between adjacent signal lines. These ground lines act as shields that reduce electromagnetic coupling and crosstalk between signal lines, enabling closer routing spacing while maintaining signal integrity. The ground lines serve as a mediating element that allows high-density routing without the harmful crosstalk effect.
3Object-generated harmful factors
If ground lines are inserted between signal lines to reduce crosstalk, then crosstalk is reduced, but device complexity increases
Solution Approach 1:
The patent designs the metal layer to serve multiple functions simultaneously: it provides signal routing, ground reference, and crosstalk shielding all within the same layer structure. By making the metal layer universal and multi-functional, the patent reduces overall device complexity compared to having separate dedicated structures for each function.
Solution Approach 2:
The patent optimizes the width, spacing, and positioning parameters of signal lines and ground lines to achieve effective crosstalk reduction while minimizing the additional area and structural complexity. By carefully tuning these geometric parameters, the patent achieves crosstalk mitigation with minimal impact on device complexity.
Data Source
AI summary
A semiconductor package according to the present disclosure includes a routing structure, a first die and a second die disposed over the routing structure, a first array of contact features disposed along a first direction and electrically coupling the first die to the routing structure, and a second array of contact features disposed along the first direction and electrically coupling the second die to the routing structure. The routing structure includes a plurality of metal lines and each of the plurality of metal lines electrically connects one of the first array of contact features and one of the second array of contact features. Each of the plurality of metal lines comprises at least two 90-degree turns on a horizontal plane.