Integrated Circuit Package Bonding With Bevel-Cleaned Dielectric Edges
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving efficient and cost-effective packaging techniques for semiconductor dies as the demand for smaller and more integrated electronic devices increases, necessitating innovative methods to reduce manufacturing cycle times and costs while improving bonding performance.
Innovation Solution
A method involving the attachment of semiconductor devices to a carrier substrate, encapsulation in a dielectric layer, bevel clean process, and formation of oxide layers on sidewalls to facilitate dielectric-to-dielectric and metal-to-metal bonding, reducing the number of fabrication steps and enhancing bonding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional packaging techniques are used for semiconductor dies, then manufacturing processes are well-established, but manufacturing cycle times are long and costs are high
Solution Approach 1:
The patent combines multiple fabrication steps into integrated processes. Specifically, the carrier substrate serves dual purposes as both a support structure during manufacturing and a final package component, eliminating the need for separate substrate attachment steps. The dielectric layer formation and bonding surface preparation are performed in an integrated sequence, reducing the total number of discrete manufacturing operations and cycle time.
Solution Approach 2:
The patent performs preliminary preparation of bonding surfaces by forming oxide layers on the carrier substrate and dielectric layers on the wafer before the actual bonding operation. The bevel clean process is also performed in advance to ensure proper bonding surfaces. These preliminary actions are completed while components are still in wafer form, allowing for more efficient subsequent bonding and reducing overall manufacturing time.
2Reliability
If advanced bonding techniques are implemented to improve bonding performance, then bonding strength is enhanced, but the number of fabrication steps increases
Solution Approach 1:
The patent employs parameter changes by forming oxide layers with specific thicknesses (e.g., 50-200 nm) on bonding surfaces to optimize bonding performance. The bevel clean process uses controlled etching parameters to remove contaminants while preserving surface integrity. These parameter optimizations enhance bonding strength without requiring additional fabrication steps, as the oxide formation and cleaning are integrated into the existing process flow.
Solution Approach 2:
The patent introduces oxide layers as intermediary bonding surfaces between the carrier substrate and wafer. These oxide layers serve as mediating interfaces that facilitate strong dielectric-to-dielectric and metal-to-metal bonds. The oxide intermediary enables reliable bonding while the process remains integrated with existing fabrication steps, avoiding the need for separate specialized bonding operations.
3Reliability
If edge topography is improved to enhance bonding performance, then bonding reliability increases, but additional processing steps are required
Solution Approach 1:
The bevel clean process is performed as a preliminary step before bonding to prepare the edge topography of the carrier substrate and wafer. This process removes contaminants and oxides from beveled edges, ensuring clean bonding surfaces. By performing this preparation in advance as part of the integrated process flow rather than as a separate post-bonding operation, the patent achieves improved bonding reliability without adding net processing steps.
Solution Approach 2:
The bevel clean process is merged with the oxide formation process, where the same processing equipment and conditions used for oxide deposition are utilized to perform the bevel cleaning function. This combination eliminates the need for a separate dedicated bevel cleaning step while still achieving the desired edge topography improvement for enhanced bonding reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing cycle times, lowers costs, and improves bonding performance by creating improved edge topographies, allowing for more efficient integration of semiconductor devices.
Implementation Method 1
performing a bevel clean process to remove portions of the gap-filling dielectric from the edge of the carrier substrate
Implementation Method 2
depositing an oxide layer on the outer sidewall of the carrier substrate and the outer sidewall of the gap-filling dielectric
Implementation Method 3
bonding a wafer to the first dielectric layer and the first bonding layer, where the wafer includes a semiconductor substrate and a second dielectric layer on an outer sidewall of the semiconductor substrate, and where bonding the wafer to the first dielectric layer includes forming a dielectric-to-dielectric bond between the first dielectric layer and the second dielectric layer
Implementation Method 4
forming a dielectric-to-dielectric bond between the first dielectric layer and the second dielectric layer
Data Source
AI summary
A method includes bonding an integrated circuit die to a carrier substrate, forming a gap-filling dielectric around the integrated circuit die and along the edge of the carrier substrate, performing a bevel clean process to remove portions of the gap-filling dielectric from the edge of the carrier substrate, after performing the bevel clean process, depositing a first bonding layer on the gap-filling dielectric and the integrated circuit die, forming a first dielectric layer on an outer sidewall of the first bonding layer, an outer sidewall of the gap-filling dielectric, and the first outer sidewall of the carrier substrate; and bonding a wafer to the first dielectric layer and the first bonding layer, wherein the wafer comprises a semiconductor substrate and a second dielectric layer on an outer sidewall of the semiconductor substrate.