Package Stack Structure Via Plugs Thermal Management
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Solution Overview
Problem
Current package stack structures face challenges in achieving high integration density and minimizing electronic systems while maintaining reliable electrical and thermal connections, as well as efficient heat dissipation and physical stability.
Innovation Solution
A package stack structure comprising a lower and upper package with via plugs electrically connecting them, a fastening element with an air space for thermal management, and a method of fabrication that includes forming molding compounds and under-fill materials to secure and isolate the semiconductor chips on substrates, allowing for reduced thickness and improved cooling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If package stack structures are used to improve integration density, then the integration density increases, but the thermal management and heat dissipation become more challenging
Solution Approach 1:
The package stack structure is divided into multiple separate packages (first package, second package, third package) stacked vertically, with each package containing its own semiconductor chip and molding compound. This segmentation allows independent thermal management for each package while achieving high integration density through vertical stacking.
Solution Approach 2:
Via plugs are introduced as intermediary conductive elements that penetrate through the molding compounds to establish electrical and thermal connections between different packages. These via plugs serve as mediators that enable heat transfer across package boundaries while maintaining electrical connectivity.
2Volume of moving object
If multiple packages are stacked to minimize electronic system size, then the system volume decreases, but the manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into independent steps for each package, allowing parallel fabrication of multiple packages before stacking. Each package can be manufactured separately with standard processes, reducing overall manufacturing complexity compared to creating a monolithic multi-chip structure.
Solution Approach 2:
Packages are prepared in advance with pre-formed molding compounds and pre-positioned via plugs before the final stacking operation. This preliminary preparation of individual packages simplifies the overall assembly process and enables modular manufacturing approaches.
3Reliability
If via plugs are used to electrically connect packages, then the electrical connectivity improves, but the manufacturing precision requirements increase
Solution Approach 1:
The via plugs are designed to self-align and self-assemble during the stacking process, utilizing the inherent geometric features of the package substrates and molding compounds to guide proper positioning without requiring ultra-precise external alignment equipment.
Solution Approach 2:
The via plugs are designed as simple, robust conductive elements that can be manufactured with standard tolerances and do not require ultra-precise positioning, making the manufacturing process more feasible and cost-effective while still achieving reliable electrical connectivity.
Data Source
AI summary
A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.


