Package Stacking Interconnects for Warpage Mitigation

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Solution Overview

Problem

Current package-on-package (PoP) stacking techniques face limitations due to limited space between stacked packages, leading to potential damage from thermal expansion and warping, which complicates assembly and reduces reliability.

Innovation Solution

The method involves forming a base package with a substrate and integrated circuit die, surrounded by stacking interconnects, and a stacked package with interconnects that attach to the base package's interconnects, forming a solder column through reflow, enhancing electrical connectivity and reducing warpage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If package-on-package stacking is implemented to increase packaging density, then packaging density is improved, but the limited space between stacked packages causes thermal expansion and warping that damages die and interconnects

Engineering Contradiction:
Improvepackaging densityVSAvoidpackage reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent implements package-on-package stacking where a second package is mounted on top of a first package, creating a nested vertical arrangement. This nesting approach increases packaging density by utilizing the vertical dimension while maintaining electrical interconnects between the stacked packages through controlled formation of solder columns that provide both electrical connection and mechanical tolerance for thermal expansion.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent forms solder columns with controlled height and composition (including copper core and solder alloy layers) that act as cushioning elements between the stacked packages. These pre-formed interconnect structures accommodate thermal expansion and warping movements that occur during operation, preventing damage to die and interconnects while maintaining reliable electrical connections.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Volume of moving object

If the space between stacked packages is reduced to improve miniaturization, then package size is decreased, but mechanical damage occurs due to warping and thermal expansion

Engineering Contradiction:
Improvepackage sizeVSAvoidmechanical damage from warping
Core Design Contradiction:
Volume of moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent reduces package footprint by stacking packages vertically in a nested configuration, minimizing the horizontal space occupied while maintaining adequate vertical clearance between packages for thermal management and mechanical tolerance.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The controlled solder column interconnects are pre-formed with specific height and material composition to provide cushioning that absorbs thermal expansion and warping stresses, preventing mechanical damage even when packages are closely stacked for miniaturization.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 3:

The interconnect structure uses composite materials including copper core for electrical conductivity and thermal management, surrounded by solder alloy layers for mechanical flexibility and thermal expansion accommodation. This composite structure provides both electrical connection and mechanical tolerance for thermal effects.

Inventive Principle:
Principle #40Composite materials

3Reliability

If conventional solder ball matrix interconnects are used for package stacking, then electrical connectivity is achieved, but the small stand-off height limits available space for base package components

Engineering Contradiction:
Improveelectrical connectivityVSAvoidavailable height for components
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent replaces conventional solder ball matrices with composite interconnect structures featuring copper cores surrounded by solder alloy layers. This composite construction provides enhanced electrical connectivity with controlled impedance while the layered structure allows for optimized height, providing sufficient stand-off for base package components such as heat spreaders and shields.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent changes the physical parameters of the interconnect structure by controlling solder column height, copper core diameter, and solder alloy composition. These parameter adjustments optimize both electrical connectivity and mechanical properties, providing adequate clearance for components while maintaining reliable electrical connections between stacked packages.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach increases packaging density, reliability, and manufacturing yield by providing high-density electrical connectivity and shielding, while minimizing warpage and mechanical damage, thus improving the assembly process and overall performance.

Implementation Method 1

forming a stacked solder column by reflowing the stacking interconnects

Methodology Applied
Scientific EffectSoldering: Soldering

Data Source

PatentUS8299595B2Integrated circuit package system with package stacking and method of manufacture thereof
Publication Date: 2012.10.30 STATS CHIPPAC MANAGEMENT PTE LTD
  • US8299595B2 patent drawing
  • US8299595B2 patent drawing
  • US8299595B2 patent drawing

AI summary

A method of manufacture of an integrated circuit package system includes: forming a base package including: fabricating a base package substrate having a component side and a system side, coupling a first integrated circuit die to the component side, and coupling stacking interconnects to the component side to surround the first integrated circuit die; forming a stacked integrated circuit package including: fabricating a stacked package substrate having a chip side, coupling a lower stacked integrated circuit die to the chip side, and attaching on a coupling side, of the stacked package substrate, the stacking interconnects; stacking the stacked integrated circuit package on the base package including the stacking interconnects of the stacked integrated circuit package on the stacking interconnects of the base package; and forming a stacked solder column by reflowing the stacked interconnects.