Semiconductor Package Stiffener Layout for Warpage and Underfill Control
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Solution Overview
Problem
Conventional semiconductor packages face challenges in preventing underfill materials from flowing outwards and contacting passive elements, and in controlling warpage defects caused by differences in thermal expansion coefficients among components.
Innovation Solution
A semiconductor package design featuring a package substrate with semiconductor chips, an interposer, passive elements, and stiffeners with varying coefficients of thermal expansion, where the stiffeners include holes and concave portions to accommodate the interposer and passive elements, preventing underfill contact and reducing warpage defects through mechanical support and thermal expansion management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If stiffeners are used to control warpage defects, then warpage control is improved, but underfill material may flow outwards and contact passive elements
Solution Approach 1:
The stiffener is segmented into multiple parts: a first stiffener with holes for passive elements, a second stiffener with a recessed portion, and a third stiffener. This segmentation creates physical barriers that prevent underfill material from flowing outward while maintaining warpage control through the distributed stiffener structure.
Solution Approach 2:
The recessed portion of the second stiffener acts as an intermediary barrier between the underfill material and the passive elements. This intermediate structure blocks the harmful flow of underfill material while allowing the stiffener system to continue functioning for warpage control.
2Device complexity
If a single stiffener structure is used, then device complexity is reduced, but it cannot effectively prevent underfill flow and control warpage simultaneously
Solution Approach 1:
The stiffener system is divided into multiple functional segments (first, second, and third stiffeners with different features) that work together to simultaneously achieve underfill containment and warpage control, resolving the contradiction between simplicity and effectiveness.
Solution Approach 2:
Different portions of the stiffener system have different local qualities: the first stiffener has holes for passive element accommodation, the second stiffener has a recessed portion for underfill blocking, and the third stiffener provides additional support. This local differentiation enables multiple functions to be achieved within the overall stiffener structure.
3Ease of manufacture
If stiffeners with uniform thermal expansion coefficient are used, then manufacturing is simplified, but warpage defects cannot be effectively controlled
Solution Approach 1:
The patent employs stiffeners with different thermal expansion coefficients (first stiffener with coefficient α1, second stiffener with coefficient α2) to match the thermal expansion characteristics of different package components. This parameter differentiation enables effective warpage control during thermal cycling while maintaining manufacturing feasibility through standard material selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively prevents underfill material contact with passive elements and reduces warpage defects by using stiffeners with different thermal expansion coefficients to manage thermal expansion differences, enhancing the reliability and mechanical stability of the semiconductor package.
Implementation Method 1
The first stiffener may have a first coefficient of thermal expansion, and the second stiffener may have a second coefficient of thermal expansion different from the first coefficient of thermal expansion
Data Source
AI summary
A semiconductor package is provided to include a package substrate, a plurality of semiconductor chips mounted on the package substrate, an interposer arranged between the package substrate and the plurality of semiconductor chips, a plurality of passive elements mounted on the package substrate and spaced apart from the interposer, a first stiffener positioned on the package substrate and including a first hole accommodating the interposer and a second hole accommodating the plurality of passive elements, and a second stiffener positioned on the first stiffener and including a third hole communicating with the first hole. The first stiffener has a first coefficient of thermal expansion, and the second stiffener has a second coefficient of thermal expansion different from the first coefficient of thermal expansion.