Multilayer Package Substrate Stress Buffer for Solder Joint Cracking
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Solution Overview
Problem
Conventional flipchip on lead packages experience high stress leading to cracking of solder joints, interlayer dielectric, and package delamination, resulting in reduced yield and reliability.
Innovation Solution
A multilayer package substrate with bump stress reduction structures (BSRS) that include dimensional changes in metal layers and dielectric layers to mitigate stress, featuring structures like swan neck, island slotting, and swiss cheese slotting to reduce cracking risk.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional flipchip on lead packages are used, then short interconnect paths and reduced package size are achieved, but high stress causes cracking of solder joints and package delamination
Solution Approach 1:
The patent applies local quality by creating bump stress reduction structures (BSRS) with specific local dimensional changes in the metal layers. These BSRS are positioned at specific locations around the solder bumps rather than uniformly across the entire package, providing localized stress relief where needed most while maintaining overall package compactness.
Solution Approach 2:
The patent implements parameter changes by introducing dimensional variations in the metal layers through BSRS. The metal layers have local physical dimension changes of at least 10% in at least one dimension, which alters the mechanical properties and stress distribution in the interconnect path without significantly increasing the overall package volume.
2Length of moving object
If conventional flipchip on lead packages are used, then short interconnect paths are achieved, but high stress causes cracking of conductive material interconnect
Solution Approach 1:
The BSRS are positioned locally around the solder bumps and conductive interconnect paths, providing targeted stress relief at critical locations rather than requiring uniform structural modifications throughout the entire interconnect path, thus maintaining short overall path length while locally enhancing strength.
Solution Approach 2:
The BSRS act as pre-configured stress buffer structures that cushion against thermal and mechanical stress before it can cause damage to the solder joints and conductive interconnect. These structures are built into the package substrate beforehand to prevent cracking rather than repair it after occurrence.
3Reliability
If conventional flipchip on lead packages are used, then reduced parasitic inductance is achieved, but high stress causes package delamination
Solution Approach 1:
The BSRS introduce controlled dimensional changes in the metal layers that alter the mechanical stress parameters without significantly affecting the electrical parameters. The local dimensional variations modify stress distribution while the overall interconnect path remains intact, preserving low parasitic inductance.
Solution Approach 2:
The package substrate incorporates multiple material layers including dielectric layers and metal layers with BSRS, creating a composite structure that combines the electrical benefits of thin interconnect paths with the mechanical benefits of stress-distributing BSRS structures.
Data Source
AI summary
A semiconductor package includes a multilayer package substrate including a top layer including a top dielectric layer and a top metal layer providing a top portion of pins on top filled vias, and a bottom layer including a bottom dielectric layer and a bottom metal layer on bottom filled vias that provide externally accessible bottom side contact pads. The top dielectric layer together with the bottom dielectric layer providing electrical isolation between the pins. And integrated circuit (IC) die that comprises a substrate having a semiconductor surface including circuitry, with nodes connected to bond pads with bonding features on the bond pads. An electrically conductive material interconnect provides a connection between the top side contact pads and the bonding features. At least a first pin includes at least one bump stress reduction structure that includes a local physical dimension change of at least 10% in at least one dimension.