Semiconductor Package Stress Testing Without Passive Device Damage
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Solution Overview
Problem
High-voltage stress testing for semiconductor devices can damage embedded passive components due to excessive testing voltage, leading to unnecessary waste and reliability concerns.
Innovation Solution
Conduct separate stress testing on the core structure and build-up structure, applying high voltage to interconnect paths without exposing embedded passive devices, followed by bonding with metal paste and glue paste, and performing low-voltage electrical tests to ensure proper connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage stress testing is applied to semiconductor devices, then device defects can be identified, but embedded passive devices may be damaged
Solution Approach 1:
The patent divides the semiconductor device into two separate structures: a core structure containing the embedded passive device, and a build-up structure containing the interconnect paths. By separating these components, high voltage stress testing can be applied selectively to the build-up structure without exposing the passive device to damaging voltages, thus identifying defects in interconnect paths while preserving the passive device integrity
Solution Approach 2:
The patent extracts the embedded passive device from the testing path by separating the core structure from the build-up structure. The passive device remains in the core structure while high voltage testing is performed on the detached build-up structure, effectively removing the harmful high voltage exposure from the passive device while still enabling comprehensive testing of the interconnect paths
2Reliability
If high voltage stress testing is applied to identify defects, then device quality can be ensured, but component waste increases
Solution Approach 1:
By segmenting the device into core and build-up structures that can be tested separately, the patent enables targeted high voltage testing of only the interconnect paths in the build-up structure. This selective testing approach identifies defects early without unnecessarily damaging passive devices, thereby reducing component waste while maintaining quality assurance
Solution Approach 2:
The patent performs high voltage stress testing on the build-up structure before bonding it to the core structure containing the passive device. This preliminary testing identifies defects in the interconnect paths early in the manufacturing process, allowing defective components to be discarded before final assembly, thus reducing waste of completed devices
Data Source
AI summary
Methods of conducting electrical tests on semiconductor packages are provided. A method according to the present disclosure includes forming a build-up structure that includes a plurality of metal layers embedded a plurality of dielectric layers, forming a core structure that embeds a passive device, performing a first electrical test on the build-up structure, performing a second electrical test on the core structure, and after performing the first electrical test and the second electrical test, bonding the build-up structure to the core structure.