Semiconductor Package Structure for Known Good Die Integration
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Solution Overview
Problem
The increasing complexity of integrated circuit packages, such as System on Integrated Chip (SoIC), poses challenges in manufacturing and testing, particularly in identifying and isolating defective dies within a wafer, which affects yield and cost optimization.
Innovation Solution
The method involves testing each die on a wafer to identify good and bad dies, followed by singulation and further processing of good dies. The dies are then mounted on a carrier with a dielectric layer and interconnected to form a semiconductor structure, which can be integrated into various package structures like InFO, CoWoS, or 3DICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple device dies are packaged in the same package to achieve more functions, then the system functionality and device performance are improved, but the complexity of manufacturing and testing increases
Solution Approach 1:
The wafer is divided into multiple individual dies, each of which can be independently tested, sorted, and packaged. This segmentation allows for modular assembly of different device types (processors, memory cubes, etc.) into a single package, achieving system functionality while managing complexity through standardized individual units.
Solution Approach 2:
The package structure is designed to accommodate multiple types of device dies (processors, memory cubes, and other components) within a single package substrate. This universal package design enables different technology nodes and device functions to be integrated together, achieving multi-functionality while using a standardized packaging platform.
2Reliability
If testing is performed on each die to identify good and bad dies, then the yield of known good dies is improved, but the manufacturing time and process complexity increase
Solution Approach 1:
Testing is performed on each die while it is still attached to the wafer, before the wafer is singulated into individual dies. This preliminary testing action identifies good and bad dies in advance, allowing only known good dies to proceed to packaging and interconnection steps, thereby improving yield without adding time to the critical packaging path.
Solution Approach 2:
The testing process is merged with the wafer-level manufacturing process rather than being a separate post-singulation step. By combining testing with the existing wafer fabrication flow, the patent achieves reliable identification of good dies without creating a separate time-consuming manufacturing stage.
3Reliability
If defective dies are isolated and removed from the wafer, then the quality of the final package is improved, but the manufacturing process complexity increases
Solution Approach 1:
Bad dies are extracted and removed from the wafer at the wafer level before singulation, leaving only known good dies to be processed further. This extraction action prevents defective dies from entering the packaging process, ensuring high package quality while simplifying downstream manufacturing by eliminating the need for individual die-level defect detection and isolation.
Solution Approach 2:
The wafer serves as an intermediary carrier that enables centralized testing and sorting of multiple dies simultaneously. By using the wafer as a mediator during the testing and sorting process, the patent achieves efficient defect isolation without requiring complex individual handling of each die, thereby maintaining manufacturing simplicity.
Data Source
AI summary
A semiconductor structure includes a first die, a dielectric layer, a second interconnection structure, a second conductive pad and a conductive feature. The first die includes a first interconnection structure over a first substrate and a first conductive pad disposed on and electrically connected to the first interconnection structure. The first conductive pad has a probe mark on a surface thereof. The dielectric layer laterally warps around the first die. The second interconnection structure is disposed on the first die and the dielectric layer, the second interconnection structure includes a conductive via landing on the first conductive pad of the first die, and the conductive via is spaced apart from the first probe mark. The second conductive pad is disposed on and electrically connected to the second interconnection structure. The conductive feature is disposed on the second conductive pad.