Semiconductor Package Structure for Thick-Chip Heat Dissipation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional chip packaging is limited by the thickness of the chip due to the need for increased conductive pillar heights for heat dissipation, which restricts the distribution density of conductive pillars and limits the thickness of the packaged chip.

Innovation Solution

A package structure with a redistribution layer, conductive pillars, an active chip, and an encapsulation layer, where the encapsulation layer has through holes of different depths to allow the active chip and conductive pillars to be electrically connected to the redistribution layer without requiring the chip thickness to exceed the pillar height, enabling increased chip thickness for improved heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If the thickness of the photoresist layer is increased to form taller conductive pillars, then the heights of the conductive pillars can be increased, but the apertures of through holes become greater which limits the distribution density of the conductive pillars

Engineering Contradiction:
Improveheight of conductive pillarVSAvoiddistribution density of conductive pillars
Core Design Contradiction:
Length of stationary objectVSManufacturing precision

Solution Approach 1:

The conductive connection path is segmented into two parts: a conductive pillar extending from the first redistribution layer, and a conductive bump on the active chip. This segmentation allows the conductive pillar height to be independent of the photoresist layer thickness, resolving the contradiction between pillar height and through-hole aperture density.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The solution transitions from a single-dimensional vertical conductive pillar to a two-dimensional connection structure involving both the conductive pillar and the conductive bump on the chip surface. This dimensional change allows the chip thickness to exceed the conductive pillar height while maintaining electrical connection.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Length of stationary object

If the thickness of the photoresist layer is limited, then the heights of the conductive pillars cannot be continuously increased, but this limits the thickness of the chip that can be packaged

Engineering Contradiction:
Improvethickness of active chipVSAvoidpackage structure complexity
Core Design Contradiction:
Length of stationary objectVSDevice complexity

Solution Approach 1:

The active chip itself provides the conductive bump structure needed for electrical connection, eliminating the need for externally added complex interconnection structures. The chip's own surface features are utilized to complete the electrical pathway, simplifying the overall package structure.

Inventive Principle:
Principle #25Self-service

3Length of stationary object

If the heights of the conductive pillars are increased to match greater chip thickness, then the chip can be packaged with greater thickness, but the apertures of through holes are greater which limits distribution density

Engineering Contradiction:
Improvethickness of active chipVSAvoiddistribution density of conductive pillars
Core Design Contradiction:
Length of stationary objectVSArea of stationary object

Solution Approach 1:

The electrical connection path is divided into the conductive pillar within the substrate and the conductive bump on the chip surface. This segmentation decouples the pillar height from the through-hole aperture size, allowing high-density pillar distribution even when chip thickness exceeds pillar height.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240030121A1Package structure and manufacturing method thereof
Publication Date: 2024.01.25 POWERTECH TECHNOLOGY INC
  • US20240030121A1 patent drawing
  • US20240030121A1 patent drawing
  • US20240030121A1 patent drawing

AI summary

A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive pillar, an active chip, an encapsulation layer, and another redistribution layer. The conductive pillar and the active chip are side by side disposed on the redistribution layer. The encapsulation layer surrounds the active chip and the conductive pillar, in which the encapsulation layer has a first through hole disposed between the active chip and the redistribution layer and a second through hole disposed between the conductive pillar and the redistribution layer, and a depth of the first through hole is less than a depth of the second through hole. The another redistribution layer is disposed on a side of the redistribution layer away from the redistribution layer and electrically connected to the redistribution layer through the conductive pillar.