Multilayer Package Substrate Adhesive Stress Mitigation

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Semiconductor devices face reliability issues due to stress applied to solder bumps between mounting substrates and semiconductor packages, particularly during thermal cycle tests, where differences in thermal expansion coefficients and elastic moduli lead to strain stress and potential cracking.

Innovation Solution

A semiconductor device design featuring a multilayer package substrate with specific thermal expansion and elastic modulus relationships between components, including a four-layer wiring structure and a thick adhesive layer, to mitigate stress on solder bumps and enhance reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional semiconductor package structure is used with standard adhesive thickness, then the device can be manufactured with standard processes, but the solder bump experiences high stress and cracking during thermal cycle tests

Engineering Contradiction:

ImproveTCT resistanceVSAvoidsolder bump stress resistance

Core Design Contradiction:

ReliabilityVSStrength

Solution Approach 1:

The patent changes the thickness parameter of the adhesive layer from conventional thin layers to a thick layer of 50-200 μm. This parameter change increases the adhesive layer's ability to absorb thermal expansion stress, reducing stress on solder bumps during thermal cycle tests and improving TCT resistance characteristics.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite structure consisting of the package substrate, thick adhesive layer, and semiconductor chip. This composite material system leverages the different mechanical properties of each layer to distribute and mitigate stress, with the thick adhesive layer acting as a stress-absorbing buffer between the substrate and chip.

Inventive Principle:

Principle #40Composite materials

2Reliability

If the adhesive layer is made thicker to reduce stress on solder bumps, then stress mitigation improves, but the overall package height increases

Engineering Contradiction:

Improvestress mitigationVSAvoidpackage substrate thickness

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The patent explicitly accepts and utilizes the parameter change in adhesive thickness (50-200 μm) as a design choice to achieve stress mitigation. The increased thickness is a deliberate modification to improve reliability, with the understanding that package height will increase accordingly.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If the package substrate and adhesive have different thermal expansion coefficients, then material selection flexibility increases, but differential thermal expansion causes stress concentration on solder bumps

Engineering Contradiction:

Improvematerial selectionVSAvoidthermal expansion stress

Core Design Contradiction:

Adaptability or versatilityVSStress or pressure

Solution Approach 1:

The thick adhesive layer serves as an intermediary between the package substrate and semiconductor chip. It mediates the differential thermal expansion by absorbing and distributing the stress that arises from mismatched thermal expansion coefficients, preventing stress concentration on the solder bumps.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent acknowledges and utilizes thermal expansion principles by designing a structure where the thick adhesive layer can accommodate differential thermal expansion between materials. The adhesive layer's mechanical properties allow it to expand and contract differently from the substrate and chip, absorbing the resulting stresses.

Inventive Principle:

Principle #37Thermal expansion

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively reduces stress on solder bumps, preventing cracking and extending the life of the semiconductor device during thermal cycle tests by allowing for better expansion and contraction alignment between substrates, thereby improving reliability and TCT resistance characteristics.

Implementation Method 1

differences in thermal expansion coefficients and elastic moduli lead to strain stress

Methodology Applied

Scientific EffectThermal expansion: Thermal Expansion

Implementation Method 2

mitigate stress on solder bumps and enhance reliability

Methodology Applied

Scientific EffectStress relaxation: Stress Relaxation

Implementation Method 3

elastic modulus relationships between components

Methodology Applied

Scientific EffectElasticity: Elasticity

Data Source

PatentUS20190067177A1Semiconductor device

Publication Date: 2019.02.28 KIOXIA CORP

AI summary

A semiconductor device includes a package substrate having a first surface and a second surface. A semiconductor chip is provided on the first surface of the package substrate and includes a semiconductor element. An adhesive is provided between the semiconductor chip and the package substrate. A metal bump is provided on the second surface. A package substrate is a multilayer substrate that includes first to fourth wiring layers and first to third resin layers. CTE1<CTE2<CTE3<CTE4 is satisfied where coefficients of thermal expansion of the semiconductor chip, the first to third resin layers, the first to fourth wiring layers, and the adhesive are CTE1 to CTE4, respectively. EM1>EM3>EM2>EM4 is satisfied where elastic moduli of the semiconductor chip, the first to third resin layers, the first to fourth wiring layers, and the adhesive are EM1 to EM4, respectively.