Package Substrate Alignment Openings for Dense Terminal Assembly

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Solution Overview

Problem

The high density of connection terminals in semiconductor packages makes it difficult to mount them within electronic devices, particularly in smaller, more multifunctional devices with increased capacity.

Innovation Solution

A package substrate design featuring a solder resist layer with specific openings and alignment patterns allows for precise alignment and secure electrical connections, utilizing wiring patterns and vias to connect semiconductor chips efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the density of connection terminals is increased to achieve higher integration, then the capacity and functionality of semiconductor packages are improved, but the difficulty of mounting and assembly increases

Engineering Contradiction:

Improvenumber of connection terminalsVSAvoidmounting difficulty

Core Design Contradiction:

Quantity of substanceVSEase of manufacture

Solution Approach 1:

The package substrate is divided into distinct regions including a chip attachment region with connection terminals and a peripheral region with alignment patterns. This segmentation allows different functional areas to be optimized independently, with alignment patterns positioned away from dense terminal regions to facilitate easier positioning during assembly without interfering with high-density terminal arrangements

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Alignment patterns are pre-formed on the package substrate before chip attachment. These patterns serve as preliminary positioning guides that enable accurate chip placement even when connection terminals are densely packed, thereby facilitating easier mounting despite high terminal density

Inventive Principle:

Principle #10Preliminary action

2Ease of manufacture

If alignment patterns are covered by solder resist like connection pads, then the manufacturing process is simplified, but alignment accuracy during chip attachment deteriorates

Engineering Contradiction:

Improveprocess simplicityVSAvoidalignment accuracy

Core Design Contradiction:

Ease of manufactureVSMeasurement precision

Solution Approach 1:

The solder resist layer is applied selectively: it covers the chip attachment region including connection terminals but leaves the peripheral region with alignment patterns exposed. This local differentiation allows connection terminals to have uniform solder resist coverage for reliable electrical connections, while alignment patterns remain exposed to provide accurate visual or optical alignment references during chip attachment

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250364430A1Package substrates and semiconductor packages having the same

Publication Date: 2025.11.27 SAMSUNG ELECTRONICS CO LTD

AI summary

A package substrate includes at least one substrate base, a plurality of wiring patterns disposed on an upper surface and a lower surface of the at least one substrate base and extending in a horizontal direction, a plurality of wiring vias extending in a vertical direction through the at least one substrate base and electrically connecting two wiring patterns positioned at different vertical levels among the plurality of wiring patterns, to each other, and an upper surface solder resist layer having a plurality of first upper surface openings extending from the upper surface to the lower surface, and at least two upper surface openings having a second opening width as a horizontal width that is greater than a first opening width which is a horizontal width of the plurality of first upper surface openings, the upper surface solder resist layer covering an upper surface of the at least one substrate base.