Package Substrate Bonding Pad Placement for Compact Semiconductor Packages
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Solution Overview
Problem
The challenge in semiconductor packaging is the increase in size or planar area due to the need for vias at the edges of multi-layered substrates to connect circuit interconnection lines, which limits the compactness and efficiency of high-capacity semiconductor packages.
Innovation Solution
The solution involves a package substrate design with strategically positioned bonding pads and vias, where the first bonding pad is closer to the chip attachment region and the second bonding pad is farther away, allowing for efficient electrical connections without the need for vias at the edges, thereby reducing the package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vias are disposed at edges of multi-layered substrate to connect circuit interconnection lines, then electrical connection between layers is achieved, but planar area of semiconductor package increases
Solution Approach 1:
The patent moves bonding pads from the edge region (2D plane) to the corner regions of the substrate, utilizing the vertical dimension and angular spaces that were previously underutilized. This dimensional repositioning allows via connections to be made at corners rather than edges, effectively reducing the planar footprint while maintaining electrical connectivity between circuit interconnection lines.
Solution Approach 2:
The patent segments the bonding pad configuration into multiple corner regions rather than concentrating connections at edge regions. By distributing bonding pads across multiple corners of the substrate, the design achieves better space utilization and reduces the overall planar area required for via connections, while maintaining all necessary electrical pathways.
2Adaptability or versatility
If multi-layered substrates are used for high capacity semiconductor packages, then circuit interconnection capability is improved, but package size increases
Solution Approach 1:
The patent exploits the corner regions of the multi-layered substrate as additional connection zones, transitioning from traditional edge-based via placement to corner-based placement. This dimensional shift enables more efficient routing of circuit interconnection lines across multiple layers without proportionally increasing the package's planar dimensions.
Solution Approach 2:
The patent applies different spatial configurations to different regions of the substrate: edge regions maintain their traditional structure while corner regions are specifically optimized with bonding pads and via holes for enhanced connection efficiency. This localized optimization allows the multi-layered substrate to achieve high circuit interconnection capability while minimizing overall package size.
Data Source
AI summary
A package substrate includes a core layer, first external interconnection lines on a top surface of the core layer, and internal interconnection lines. The first external interconnection lines include a first outermost external interconnection line on an edge of the core layer, and the internal interconnection lines include an outermost internal interconnection line in the edge of the core layer. A first bonding pad is disposed on the first outermost external interconnection line and exposed in a first bonding region of the core layer. A second bonding pad is disposed on the outermost internal interconnection line and exposed in a second bonding region of the core layer. The first bonding region is spaced apart from a chip attachment region by a first distance, and the second bonding region is spaced apart from the chip attachment region by a second distance greater than the first distance.