Package Substrate Byte-Row Layout for Higher DDR Area Utilization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in DDR IC chips is optimizing the arrangement of multiple byte region rows to improve area utilization, as increasing the number of rows leads to inefficient use of the active surface.
Innovation Solution
A package substrate design with multiple circuit layers and conductive vias, where byte region rows are arranged side by side sequentially from the edge to the center, with pads extending through traces of circuit layers closer to the substrate surface, allowing for increased rows without increasing the chip's edge length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the number of byte region rows is increased, then the area utilization of the IC chip is improved, but the arrangement complexity and space management difficulty increase
Solution Approach 1:
The patent extends the byte region arrangement from a two-dimensional surface layout to a three-dimensional structure by routing pads through multiple circuit layers. Pads from byte regions are connected via traces on different layers (first circuit layer, second circuit layer, third circuit layer), allowing vertical stacking of byte region rows without increasing the chip's planar footprint. This dimensional transition enables denser packing of byte regions while maintaining manageable arrangement complexity through systematic layer-based routing.
2Area of moving object
If more byte region rows are arranged side by side, then the area utilization is improved, but the edge length of the chip increases
Solution Approach 1:
Instead of arranging byte region rows in a single plane which would increase edge length, the patent utilizes multiple circuit layers stacked vertically. Pads from byte regions are routed through traces on different layers (first, second, and third circuit layers), effectively moving the arrangement into the vertical dimension. This allows multiple byte region rows to be packed within the same planar footprint without extending the chip's edge length, as the additional rows are accommodated through vertical layering rather than horizontal expansion.
Solution Approach 2:
The patent implements a nested structure where circuit layers are stacked within each other vertically. The first circuit layer contains pads and traces for byte regions, the second circuit layer provides intermediate routing, and the third circuit layer offers additional routing paths. This nested arrangement of circuit layers allows byte region rows to be densely packed by nesting their electrical connections within the multi-layer structure, preventing edge length increase while maximizing area utilization.
3Area of moving object
If pads are extended through multiple circuit layers, then the area utilization is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent divides the routing function across multiple segmented circuit layers, with each layer handling specific portions of the pad connections. The first circuit layer handles pads and initial traces, the second circuit layer provides intermediate routing paths, and the third circuit layer completes the connections. This segmentation of the routing path into discrete layers simplifies manufacturing by allowing each layer to be fabricated and routed independently, reducing the overall manufacturing complexity compared to attempting to route all connections on a single complex layer.
Solution Approach 2:
By transitioning pad routing from a two-dimensional single-layer approach to a three-dimensional multi-layer approach, the patent distributes routing complexity across multiple layers rather than concentrating it on one layer. This dimensional change allows for simpler trace patterns on each individual layer while achieving the same overall connectivity, thereby reducing manufacturing complexity despite the increased number of layers.
Data Source
AI summary
A package substrate has a substrate surface and a chip region on the substrate surface. The package substrate includes circuit layers, conductive vias, and byte region rows. The circuit layers are sequentially spaced below the substrate surface. Each conductive via is connected to at least two of the circuit layers. The byte region rows are arranged side by side sequentially from an edge of the chip region to a center of the chip region, and each byte region row includes byte regions arranged in a row. Each byte region includes pads located on the circuit layer closest to the substrate surface. The pads of the byte regions of the byte region row closer to the edge of the chip region extend from the chip region to an outside of the chip region through traces of the circuit layer closer to the substrate surface.