Package Substrate Circuit Patterns Etching Segmentation

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Solution Overview

Problem

Current dry film etching processes for manufacturing circuit lines face challenges in achieving uniformity and thickness below 35/35 μm, leading to issues such as over etching, broken lines, and micro-shorts, which result in low yield and difficulty in repairing fine circuit lines.

Innovation Solution

A method involving a first copper layer with protrusions formed by dry film etching, followed by lamination of a dielectric layer and formation of a double copper layer structure, with the second copper layer etched to create trapezoidal circuit patterns, and subsequent polishing to adjust linewidth and distance between patterns, forming embedded and surface circuit layers with electrically conductive poles for coupling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If dry film etching process is used to manufacture circuit lines, then the process is short and low cost, but the circuit line thickness and uniformity cannot be controlled below 35/35 μm

Engineering Contradiction:
Improveprocess simplicity and costVSAvoidcircuit line thickness and uniformity
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent divides the single etching process into multiple sequential etching steps with different etching solutions. The first etching solution removes oxide layers and partially etches the copper layer, while the second etching solution completes the etching process. This segmentation allows precise control over etching depth and circuit line dimensions, achieving thickness and uniformity below 35/35 μm while maintaining process simplicity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameters of the etching process by using different etching solutions with specific compositions and concentrations for different etching stages. The first etching solution contains specific chemicals for oxide removal and initial copper etching, while the second etching solution is optimized for precise final etching. This parameter optimization enables precise control of circuit line thickness and uniformity.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If dry film etching is used for fine circuit lines, then manufacturing cost is reduced, but over etching occurs resulting in thin or broken circuit lines

Engineering Contradiction:
Improvemanufacturing costVSAvoidcircuit line integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent segments the etching process into multiple controlled stages. The first etching solution performs oxide removal and partial copper etching, creating a controlled depth profile. The second etching solution then completes the etching with precise control. This segmentation prevents over-etching by limiting each stage's etching depth, ensuring circuit line integrity and preventing broken lines.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary oxide removal and partial etching in the first etching stage before completing the process. This preliminary action prepares the surface and establishes a controlled etching profile, preventing excessive etching in subsequent stages and ensuring circuit line integrity while maintaining cost-effectiveness.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If dry film etching is used for fine circuit lines, then process cost is reduced, but micro-shorts occur due to insufficient etching control

Engineering Contradiction:
Improveprocess costVSAvoidetching depth control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent divides the etching process into two distinct stages with different etching solutions. The first stage performs oxide removal and initial copper etching with controlled depth, while the second stage completes the etching with precise depth control. This segmentation ensures accurate etching depth control, preventing micro-shorts by avoiding both over-etching and under-etching, while maintaining cost reduction.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent optimizes parameters by using different etching solution compositions and concentrations for each etching stage. The first etching solution is formulated for oxide removal and initial copper etching, while the second etching solution is optimized for precise final etching control. This parameter optimization achieves accurate etching depth control, preventing micro-shorts while maintaining cost-effectiveness.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the manufacturing of package substrates with improved uniformity and thickness control, reducing the likelihood of over etching and micro-shorts, thereby increasing yield and facilitating the production of finer circuit lines.

Implementation Method 1

A first copper layer is etched to form a plurality of protrusions

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

a dielectric layer is laminated on these protrusions to embed first circuit patterns

Methodology Applied
Scientific EffectLamination: Lamination

Data Source

PatentUS10412835B2Package substrate
Publication Date: 2019.09.10 LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY QINHUANGDAO CO LTD
  • US10412835B2 patent drawing
  • US10412835B2 patent drawing
  • US10412835B2 patent drawing

AI summary

A package substrate includes a dielectric layer, a first circuit layer, a second circuit layer and at least one electrically conductive pole. The dielectric layer includes a first side and a second side opposite to the first side. The first circuit layer is located at the first side of the dielectric layer, and includes a plurality of spaced first circuit patterns embedded into the dielectric layer. The second circuit layer is located at the second side of the dielectric layer, and includes a plurality of spaced second circuit patterns located on the second side the dielectric layer. The electrically conductive pole electrically couples the first circuit layer to the second circuit layer. Each of the first circuit patterns has an extension direction from the first side toward the second side, and has widths gradually decreasing along the extension direction.