Package Substrate Structure with Conductive Pillars and Adhesive Layer

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current semiconductor packaging technologies face challenges with high temperature and pressure requirements for copper bonding, complex manufacturing processes, and asymmetric structure-induced warpage, leading to increased costs and reduced manufacturing yield.

Innovation Solution

A package substrate structure and bonding method utilizing conductive pillars and an adhesive layer between substrates, allowing for low-temperature bonding with reduced process requirements, eliminating the need for chemical polishing and annealing, and addressing warpage issues through stress concentration points.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If copper bonding is used to reduce resistance in fine circuit lines, then electrical resistance is reduced, but bonding temperature must be increased to 300-450°C with pressure up to 300 MPa and annealing process required

Engineering Contradiction:
Improveelectrical resistanceVSAvoidbonding temperature
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent changes the bonding parameters by using a eutectic bonding interface (such as Au-Sn or Cu-Sn system) that enables bonding at lower temperatures (around 200-300°C) compared to traditional copper-copper bonding (300-450°C). This is achieved by selecting materials with eutectic composition that have lower melting points, allowing bonding to occur at reduced temperature while maintaining electrical conductivity and mechanical strength

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs composite material structures where a eutectic bonding layer (e.g., Au-Sn intermetallic compound) is formed between bonding surfaces. This composite structure combines the low melting point advantage of eutectic materials with the electrical conductivity requirements, enabling low-temperature bonding while maintaining reliable electrical connection in fine circuit lines

Inventive Principle:
Principle #40Composite materials

2Manufacturing precision

If chemical polishing process (CMP) is used to clean copper surface for bonding, then bonding surface quality is improved, but manufacturing process complexity increases and manufacturing cost cannot be reduced

Engineering Contradiction:
Improvebonding surface flatnessVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent uses a sacrificial organic layer (such as photoresist or organic adhesive layer) that is disposed of after serving its bonding function. This disposable layer provides surface flatness during bonding and is subsequently removed, eliminating the need for complex CMP processes. The organic layer acts as a temporary placeholder that simplifies the manufacturing process while achieving the required bonding surface quality

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent introduces an organic intermediary layer between the bonding surfaces that mediates the bonding process. This layer provides a flat bonding surface during the bonding operation and is later removed, serving as a temporary mediator that simplifies surface preparation without requiring complex polishing processes

Inventive Principle:
Principle #24Intermediary (Mediator)

3Adaptability or versatility

If asymmetric structure is produced when fine circuit lines are formed on substrate, then circuit functionality is achieved, but warpage on substrate material occurs resulting in poor manufacturing yield

Engineering Contradiction:
Improvecircuit line configurationVSAvoidsubstrate warpage
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent applies local quality by placing reinforcement structures (such as additional conductive pillars, support vias, or stiffening layers) specifically at locations where warpage is most likely to occur due to asymmetric circuit line distributions. This localized reinforcement maintains the required asymmetric circuit functionality while providing structural support to prevent substrate warpage in critical areas

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses counterweight structures (such as added mass or stiffness in specific locations) to balance the asymmetric stress distribution caused by fine circuit line formations. These counterweight elements are strategically positioned to offset the warpage-inducing forces, maintaining substrate flatness while preserving the necessary asymmetric circuit configuration

Inventive Principle:
Principle #8Anti-weight (Counterweight)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach achieves favorable bonding strength, quality, and electrical properties while reducing manufacturing costs and improving yield by enabling low-temperature bonding and eliminating the need for complex processes like chemical polishing and annealing.

Implementation Method 1

An adhesive layer is disposed between the first substrate and the second substrate, and the adhesive layer fills gaps between the conductive pillars

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS10658282B2Package substrate structure and bonding method thereof
Publication Date: 2020.05.19 UNIMICRON TECH CORP
  • US10658282B2 patent drawing
  • US10658282B2 patent drawing
  • US10658282B2 patent drawing

AI summary

A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.