Package Substrate Layout That Cuts Copper Waste During Dicing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integrated circuit (IC) packaging industry generates significant waste, particularly copper waste, which poses environmental pollution concerns, and existing methods fail to effectively reduce metal waste during the packaging process.
Innovation Solution
A package substrate and method for fabricating chip assemblies where substrate conductors are arranged outside scribe lines, and alignment marks are provided on paths that do not overlap with scribe lines, allowing for precise alignment during die bonding and dicing while minimizing metal waste generation, using a resin dicing blade and redundant conductors in non-overlapping regions for warpage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If substrate conductors are arranged in scribe line regions, then alignment and electrical connection are facilitated, but metal waste is generated during dicing process
Solution Approach 1:
The substrate surface is divided into distinct functional regions: die-bonding regions for chip mounting and scribe line regions for dicing separation. By segmenting the substrate layout, conductors can be positioned in die-bonding regions while scribe lines remain metal-free, eliminating metal waste during dicing while maintaining electrical connectivity in functional areas.
Solution Approach 2:
Metal conductors are extracted from the scribe line regions and relocated to die-bonding regions. This extraction eliminates the source of metal waste during dicing, as the scribe lines now contain only non-metallic material that can be cleanly separated without generating copper or metal particulate pollution.
2Manufacturing precision
If alignment marks are placed on scribe lines, then dicing alignment is improved, but metal particles are released during dicing
Solution Approach 1:
Alignment marks are introduced as intermediary features positioned in scribe line regions. These marks serve as reference points for dicing alignment without requiring metal conductors in the scribe lines. The alignment marks can be made of non-metallic materials or patterns that provide visual or optical reference without generating harmful metal particles during the dicing process.
3Loss of substance
If conductors are placed in die-bonding regions only, then metal waste is reduced, but alignment precision may be compromised
Solution Approach 1:
The substrate design integrates multiple functions into different regions: die-bonding regions provide both electrical connectivity through conductors and chip mounting functionality, while scribe line regions provide dicing separation and alignment reference through non-metallic alignment marks. This multi-functional regional design maintains alignment precision without requiring conductors in scribe lines.
Data Source
AI summary
A package substrate and a method for fabricating a chip assembly are provided. The method includes: providing a substrate, which has an upper substrate surface and a lower substrate surface, the upper substrate surface is divided into a plurality of scribe line regions that define a plurality of die-bonding regions, and any adjacent two of the die-bonding regions are separated by the scribe line regions. The die-bonding region is provided with a substrate conductor and a core material body, the substrate conductor penetrates the substrate and has upper and lower conductive ends exposed on the upper and lower substrate surfaces, respectively, and the core material body is disposed adjacent to the substrate conductor in the substrate. The method further includes: fixing chips in the die-bonding regions, respectively; and performing a dicing process along a plurality of scribe lines defined by the scribe line regions to form chip assemblies.