Package Substrate Ground Pattern Layout for Signal Delay Matching
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Solution Overview
Problem
Existing semiconductor packages face issues with varying signal transmission delays due to differences in the length of interconnection patterns, leading to inconsistent signal reception times by the semiconductor chip.
Innovation Solution
The package substrate design includes interconnection patterns with a first pattern extending in a first direction and protruding second patterns in a perpendicular direction, surrounded by power interconnection patterns providing a ground voltage, which increases capacitance and adjusts delay times to align with clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the physical length of interconnection patterns is increased to reduce signal transmission delay, then signal transmission delay is reduced, but the area of the package substrate increases
Solution Approach 1:
The patent changes the electrical parameters of the interconnection patterns by introducing ground patterns adjacent to signal patterns. This creates parasitic capacitance between the signal and ground patterns, which slows down signal propagation speed. By adjusting the density and configuration of ground patterns, the effective electrical length of the interconnection can be extended without increasing the physical length, thereby reducing signal transmission delay while maintaining a compact substrate area.
Solution Approach 2:
The ground patterns serve as an intermediary element between signal patterns. These ground patterns are not directly carrying signals but create an electromagnetic field interaction that modifies the signal propagation characteristics. The ground patterns act as a mediator that introduces controlled capacitance to adjust signal delay timing without requiring longer physical trace lengths.
2Loss of time
If interconnection patterns are made longer to compensate for position differences, then signal transmission delay is reduced, but the complexity of the interconnection pattern design increases
Solution Approach 1:
Instead of uniformly increasing the length of all interconnection patterns, the patent applies ground patterns locally adjacent to specific signal patterns that require delay adjustment. This local modification approach allows selective tuning of signal delay for individual signal paths without redesigning the entire interconnection network, thereby reducing design complexity while achieving the desired delay compensation.
Solution Approach 2:
The patent modifies the electrical characteristics of interconnection patterns by adding ground patterns, which changes the capacitance and propagation speed parameters. This allows delay compensation through parameter adjustment rather than geometric modification, simplifying the overall pattern design while achieving timing alignment.
3Loss of time
If ground layers are added to increase capacitance, then signal delay is adjusted, but the number of layers and manufacturing complexity increases
Solution Approach 1:
The patent combines the ground patterns with existing power supply patterns or substrate structures, merging multiple functions into a single structural element. By integrating ground patterns with power patterns or substrate ground planes, the design achieves the required capacitance for delay adjustment without adding separate dedicated ground layers, thereby reducing manufacturing complexity while maintaining the desired electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces or eliminates differences in signal delay times, ensuring consistent signal reception and preventing deterioration of signal characteristics without increasing the physical length of the interconnection patterns, facilitating miniaturization and improved signal integrity.
Implementation Method 1
At least one power interconnection pattern among the power interconnection patterns surrounds the at least one signal interconnection pattern. The at least one power interconnection pattern has a shape corresponding to the first pattern and the plurality of second patterns. The at least one power interconnection pattern is a supply path for a ground voltage.
Data Source
AI summary
A package substrate includes a base substrate. Upper pads are disposed on an upper surface of the base substrate. Lower pads are disposed on a lower surface of the base substrate. A plurality of interconnection patterns respectively connect the upper pads and the lower pads to each other. The plurality of interconnection patterns includes signal interconnection patterns and power interconnection patterns. At least one signal interconnection pattern includes a first pattern extending in a first direction and a plurality of second patterns protruding from the first pattern in a second direction perpendicular to the first direction. At least one power interconnection pattern surrounds the at least one signal interconnection pattern and has a shape corresponding to the first pattern and the plurality of second patterns. The at least one power interconnection pattern is a supply path for a ground voltage.