Package Substrate Assembly With Non-Solder Die Interconnects

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Solution Overview

Problem

Conventional substrates for integrated circuit dies are limited by manufacturing, materials, and thermal considerations, constraining interconnect pitch and hindering efficient communication and power delivery between dies.

Innovation Solution

The use of a package substrate with conductive pathways and non-solder interconnects, such as DTPS and DTD interconnects, allows for secure attachment and efficient communication between multiple IC dies, supporting high-density interconnects and improved power delivery while accommodating differential thermal expansion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional substrates are used for coupling integrated circuit dies, then mechanical stability is achieved, but interconnect pitch is constrained by manufacturing, materials, and thermal considerations

Engineering Contradiction:
Improveinterconnect pitchVSAvoidmanufacturing constraints
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent changes the material parameters of the substrate, transitioning from conventional substrates to a glass substrate with specific properties (low thermal expansion coefficient, high thermal conductivity). This parameter change enables finer interconnect pitch while maintaining manufacturability and thermal performance

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a composite substrate structure combining glass with metal interconnect layers and dielectric materials. This composite approach allows the substrate to simultaneously provide mechanical stability, thermal management, and support for high-density interconnects

Inventive Principle:
Principle #40Composite materials

2Power

If conventional substrates are used, then assembly is simplified, but thermal management and power delivery are insufficient for high-density interconnects

Engineering Contradiction:
Improvepower deliveryVSAvoidthermal management
Core Design Contradiction:
PowerVSTemperature

Solution Approach 1:

The patent changes the thermal parameters of the substrate by using glass with high thermal conductivity, enabling effective heat dissipation for high-density interconnects. The thermal conductivity parameter is specifically optimized to manage heat generated by multiple closely-spaced dies

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The glass substrate serves multiple functions simultaneously: it provides mechanical support, thermal management, electrical isolation, and a platform for high-density interconnects. This multi-functionality resolves the contradiction between simplified assembly and advanced thermal/power capabilities

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If multiple IC dies are attached with secure attachment, then reliability is improved, but cost increases and design flexibility decreases

Engineering Contradiction:
Improveattachment reliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the attachment process into standardized steps: die attachment to the glass substrate, followed by wire bonding. This segmentation allows for reliable attachment while maintaining cost-effectiveness through process standardization and modularity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The glass substrate acts as an intermediary platform between multiple dies and the final package. It provides a stable, standardized interface that simplifies the attachment process and reduces overall manufacturing cost while maintaining high reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12412881B2Microelectronic assemblies
Publication Date: 2025.09.09 INTEL CORP
  • US12412881B2 patent drawing
  • US12412881B2 patent drawing
  • US12412881B2 patent drawing

AI summary

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.