3D Package Substrate With Embedded Capacitor Dies for Voltage Stability

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Solution Overview

Problem

The miniaturization of logic components leads to decreased operating voltages, resulting in a smaller tolerance for voltage variations, which causes significant voltage fluctuations during power transmission, diminishing the stability and performance of logic components.

Innovation Solution

A package substrate is designed with a core layer that includes a plurality of semiconductor dies stacked one above another, with at least one die being a capacitor die electrically connected to electrical interconnects in the dielectric layers, providing embedded capacitor functionality for improved power management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If logic components are miniaturized to improve integration density, then productivity and device complexity are improved, but voltage tolerance decreases and voltage fluctuations increase

Engineering Contradiction:
Improveintegration densityVSAvoidvoltage tolerance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from planar capacitor placement to three-dimensional stacking of capacitor dies within the substrate core layer. This vertical arrangement allows multiple capacitor layers to be integrated without increasing the substrate footprint, thereby maintaining high integration density while providing sufficient capacitance to stabilize voltage for miniaturized logic components

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Capacitor dies are embedded within the core layer of the substrate, nesting the capacitive structures inside the substrate volume rather than placing them on the surface. This nested configuration maximizes space utilization and maintains compact form factor while improving power delivery stability

Inventive Principle:
Principle #7Nested doll (Nesting)

2Ease of operation

If power is transmitted over long traces on circuit board to deliver voltage to logic components, then ease of operation is maintained, but voltage fluctuations increase and reliability deteriorates

Engineering Contradiction:
Improvepower deliveryVSAvoidvoltage stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent implements localized power management by placing capacitor dies in close proximity to logic components within the same substrate. This local configuration creates short current paths and reduces the impact of trace inductance and resistance, thereby minimizing voltage fluctuations while maintaining ease of power delivery

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

Capacitor dies serve as intermediary energy storage elements between the power source and logic components. These capacitors act as local energy reservoirs that can rapidly supply or absorb current to compensate for voltage variations during power transmission, improving voltage stability without complicating the power delivery architecture

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250125276A1Package substrate, semiconductor device, and method for forming package substrate
Publication Date: 2025.04.17 AP MEMORY TECH CORP
  • US20250125276A1 patent drawing
  • US20250125276A1 patent drawing
  • US20250125276A1 patent drawing

AI summary

A package substrate includes a first dielectric layer, a second dielectric layer and a core layer. The first dielectric layer includes first electrical interconnect. The second dielectric layer includes second electrical interconnect. The core layer is situated between the first dielectric layer and the second dielectric layer, and includes a plurality of semiconductor dies stacked one above another between the first dielectric layer and the second dielectric layer. A first semiconductor die of the semiconductor dies is a capacitor die electrically connected to the first electrical interconnect of the first dielectric layer.