Package Substrate Circuit Layering for Fine-Line Etching Control

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Solution Overview

Problem

Existing package substrate fabrication processes face challenges in reducing side etching during copper etching, leading to line width loss and reduced circuit reliability.

Innovation Solution

The use of organic conductive layers, such as graphite, in the package substrate design allows for controlled side etching by removing these layers with a non-copper etching chemical before etching the copper, thereby reducing line width loss and achieving finer line pitches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If chemical liquid is used to etch the metal layers and copper layer simultaneously, then the etching process is simple and efficient, but the line width is reduced and line pitch is increased due to side etching, resulting in line width loss and reduced circuit reliability

Engineering Contradiction:
Improveetching efficiencyVSAvoidline width precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The etching process is segmented into two distinct steps: first etching the organic conductive layer with a non-copper etching chemical, then etching the copper layer with a copper etching chemical. This segmentation allows each etching step to be optimized independently, preventing side etching of the copper layer during the organic layer removal, thus maintaining line width precision while preserving etching efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The organic conductive layer is etched first as a preliminary action before etching the copper layer. This preliminary removal of the organic layer eliminates the source of side etching before the copper etching process begins, ensuring that the copper layer maintains its original line width and pitch dimensions

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If the circuit line width is reduced to achieve finer circuits, then the circuit density is improved, but the side etching amount becomes more significant relative to the line width, causing greater line width loss and reliability issues

Engineering Contradiction:
Improveline pitch finenessVSAvoidcircuit reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

By segmenting the etching process into separate steps for the organic layer and copper layer, the patent enables precise control over the copper etching process. This ensures that even for fine line widths, the copper layer experiences minimal side etching, maintaining both the desired fine pitch and circuit reliability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The organic conductive layer serves as an intermediary that is selectively removed first. This intermediary removal eliminates the source of side etching before the copper layer is processed, protecting the copper circuits from excessive side etching even when line widths are reduced for finer circuits

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces side etching during copper etching, allowing for the fabrication of circuit layers with finer line widths and pitches, enhancing circuit reliability and density.

Implementation Method 1

removing the organic conductive layer by using a non-copper etching chemical

Methodology Applied
Scientific EffectChemical etching:

Data Source

PatentUS20250132236A1Package substrate and fabricating method thereof
Publication Date: 2025.04.24 SILICONWARE PRECISION IND CO LTD
  • US20250132236A1 patent drawing
  • US20250132236A1 patent drawing
  • US20250132236A1 patent drawing

AI summary

A package substrate and a fabricating method thereof are provided, in which a core board body is provided, a first organic conductive layer and a second metal layer are sequentially formed on a first metal layer of the core board body, and portions of the first organic conductive layer and the first metal layer are removed respectively according to a pattern of the second metal layer, such that the second metal layer, or the second metal layer, the first organic conductive layer and the first metal layer are served as a first circuit layer. Therefore, the design of the organic conductive layer can facilitate the control of the side etching amount of the metal circuit during etching, enabling the production of circuit layer with fine line width/fine line pitch.