Package Substrate Fabrication Using Multi-Carrier Segmentation
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Solution Overview
Problem
The high fabrication cost of semiconductor embedded in substrate package substrates hinders the development of miniaturized, high-density electronic devices, necessitating a cost-effective packaging solution.
Innovation Solution
A method involving a multi-step process on carrier substrates, including forming conductive wires, dielectric layers, and connecting units, with metal pillars for interconnects, to create a Package-on-Package (PoP) substrate structure, allowing for concurrent fabrication of multiple substrates using wafer-level or panel-level packaging technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor embedded in substrate technology is used to achieve miniaturized size and reduced noise disturbance, then packaging performance is improved, but fabrication cost increases
Solution Approach 1:
The substrate is divided into multiple carrier substrates, each carrying multiple package substrates simultaneously. This segmentation allows parallel processing of multiple packages, improving manufacturing efficiency and reducing per-unit fabrication cost while maintaining the miniaturized packaging performance.
Solution Approach 2:
The invention transitions from traditional single-substrate processing to a multi-carrier substrate array configuration. By arranging multiple package substrates in spatial dimensions on carrier substrates, the system achieves high-density concurrent fabrication, reducing overall manufacturing cost while preserving packaging performance.
2Ease of manufacture
If traditional single-substrate packaging is used, then fabrication process is simple, but production efficiency is low
Solution Approach 1:
Multiple package substrates are merged onto single carrier substrates, allowing simultaneous fabrication of multiple packages in one processing cycle. This merging approach maintains relatively simple fabrication processes while dramatically improving production efficiency through parallel processing.
Solution Approach 2:
Carrier substrates are prepared in advance with pre-formed conductive wires and connecting units before package substrates are mounted. This preliminary preparation enables subsequent high-speed concurrent fabrication of multiple packages, improving production efficiency without significantly complicating the overall manufacturing process.
3Volume of moving object
If multi-layered package substrate structure is implemented to enhance miniaturization, then device density increases, but manufacturing complexity increases
Solution Approach 1:
The multi-layered structure is segmented across multiple carrier substrates, with each carrier handling a subset of package substrates. This segmentation allows complex multi-layer fabrication to be divided into manageable units, reducing per-unit manufacturing complexity while achieving high device density through parallel multi-layer construction.
Solution Approach 2:
The invention adds the spatial dimension of multiple carrier substrates to the multi-layered package structure. By distributing multi-layer fabrication across multiple carriers in parallel, the system achieves high device density without proportionally increasing manufacturing complexity, as each carrier processes a simplified subset of the total structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs by enabling the simultaneous production of multiple package substrates with a multi-layered structure, enhancing miniaturization and reducing external noise interference, while maintaining a firm and protective substrate structure.
Implementation Method 1
the second connecting unit is formed by electrolytic plating
Data Source
AI summary
This disclosure provides a package substrate fabrication method including: forming a first conductive wire and a first connecting unit on a first carrier substrate; forming a first dielectric layer on the first carrier substrate while enabling an end face of the first connecting unit to be exposed; bonding a second carrier substrate to the first dielectric layer and removing the first carrier substrate; disposing a first circuit chip and a second connecting unit on the first conductive wire; forming a second dielectric layer on the second carrier substrate while enabling the first circuit chip and the second connecting unit to be surrounded by the second dielectric layer and an end face of the second connecting unit to be exposed; forming a second conductive wire on the second dielectric layer; disposing a second circuit chip on the second conductive wire; and forming a third dielectric layer on the second carrier substrate.