Package Substrate First-Level Interconnect Architecture

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Solution Overview

Problem

The challenge in electronic devices is to accommodate an increasing number of IC die in a compact space, which is hindered by thickness variation of first-level interconnects (FLIs) leading to yield losses and coarser bump pitches, and existing planarization methods introduce additional thickness variations and performance issues.

Innovation Solution

A package substrate with a planarized layer surface and via surface, featuring a bond pad with a seed layer and a plating stack, where the seed layer is thin and the plating stack is conformal, minimizing FLI thickness variation and enabling finer pitches through chemical-mechanical planarization and conformal plating processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional planarization methods are used, then the layer surface is flattened, but additional thickness variations are introduced and performance issues occur

Engineering Contradiction:

Improvelayer surface flatnessVSAvoidperformance reliability

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent performs planarization of the via surface before depositing the seed layer and plating stack. This preliminary action ensures that the underlying surface is flat before subsequent layers are added, preventing thickness variations from propagating through the FLI structure and compromising reliability.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent applies planarization specifically to the via surface rather than the entire layer, and separately planarizes the layer surface. This localized approach addresses thickness variations only where they affect the bond pad and FLI performance, avoiding unnecessary processing that could introduce additional variations elsewhere.

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If FLI thickness variation is reduced, then finer pitches are enabled and yield loss decreases, but manufacturing complexity increases

Engineering Contradiction:

ImproveFLI thickness uniformityVSAvoidmanufacturing process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The bond pad structure is segmented into distinct layers: a planarized via surface, a thin seed layer, and a conformal plating stack. This segmentation allows each layer to be optimized independently - the via surface is planarized to provide a uniform base, the seed layer is kept thin to minimize thickness contribution, and the plating stack is applied conformally to ensure uniform thickness, collectively achieving FLI thickness uniformity while managing manufacturing complexity through systematic process breakdown.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes key parameters: reducing seed layer thickness to minimize its contribution to overall FLI thickness variation, and using conformal plating to ensure uniform thickness deposition. These parameter changes enable finer pitches and reduced yield loss while the systematic approach manages manufacturing complexity.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If more IC die are accommodated in compact space, then device functionality increases, but space-related issues and thickness variation problems worsen

Engineering Contradiction:

Improvenumber of IC die per packageVSAvoidFLI thickness control

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent addresses the two-dimensional space constraint by optimizing the vertical dimension (thickness) of the FLI. By reducing and controlling the thickness of each layer (planarized via surface, thin seed layer, conformal plating stack), the overall FLI thickness is minimized and uniformity is maximized. This vertical optimization enables finer bump pitches, allowing more IC die to be accommodated in compact space while maintaining manufacturing precision.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces FLI thickness variation, allowing for finer pitches, reducing yield loss, and enabling more IC die to be coupled with the package substrate, while maintaining reliability and performance by minimizing impedance mismatch issues.

Implementation Method 1

chemical-mechanical planarization

Methodology Applied

Scientific EffectChemical-mechanical planarization:

Implementation Method 2

conformal plating processes

Methodology Applied

Scientific EffectConformal plating: Electroplating

Data Source

PatentUS10121679B1Package substrate first-level-interconnect architecture

Publication Date: 2018.11.06 TAHOE RES LTD

AI summary

Embodiments of the present disclosure may relate to a package substrate that may include a layer having a layer surface that is planarized and a via within the layer, where the via includes a via surface that is exposed on the layer surface, and where the via surface is planarized. The package substrate may further include a bond pad on the layer surface, where a first thickness of the bond pad includes a seed layer on the via surface, and where a second thickness of the bond pad includes a plating stack on the seed layer. Other embodiments may be described or claimed.