Semiconductor Package Substrate With Communication-Hole Encapsulation

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Solution Overview

Problem

Existing semiconductor packages face challenges in easily forming an encapsulant on a package substrate to protect semiconductor chips and auxiliary chips.

Innovation Solution

A semiconductor package design that includes a package substrate with a communication hole extending from the upper surface to the lower surface, allowing an encapsulant to be easily formed around both the semiconductor chip and the auxiliary chip, and filling the communication hole.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a semiconductor chip and auxiliary chip are attached to a package substrate with separate encapsulation processes, then each chip can be protected, but the manufacturing process becomes complex and time-consuming

Engineering Contradiction:

Improvechip protectionVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the encapsulation of the semiconductor chip and auxiliary chip into a single encapsulant structure. The encapsulant is configured to simultaneously encapsulate both chips, eliminating the need for separate encapsulation processes and reducing manufacturing complexity while maintaining protection reliability

Inventive Principle:

Principle #5Merging (Combining)

2Speed

If a communication hole extends vertically through the package substrate, then signal transmission is efficient, but the package height increases

Engineering Contradiction:

Improvesignal transmission efficiencyVSAvoidpackage height

Core Design Contradiction:

SpeedVSLength of moving object

Solution Approach 1:

The patent implements a nested structure where the communication hole is positioned within the overlapping region of the semiconductor chip and auxiliary chip. This allows the communication hole to extend through the package substrate while the chips provide lateral coverage, effectively nesting the communication pathway within the chip arrangement to minimize package height

Inventive Principle:

Principle #7Nested doll (Nesting)

3Reliability

If external connection terminals are spaced apart from the auxiliary chip, then signal interference is reduced, but the package footprint increases

Engineering Contradiction:

Improvesignal interference reductionVSAvoidpackage footprint

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent utilizes the vertical dimension by positioning the external connection terminals on the lower surface of the package substrate, while the auxiliary chip is positioned on the upper surface. This spatial separation in the vertical dimension reduces signal interference without requiring increased horizontal spacing, thereby maintaining a compact package footprint

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12205925B2Semiconductor package having package substrate

Publication Date: 2025.01.21 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.