Package Substrate Differential Impedance Optimization for 25 Gbps
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Solution Overview
Problem
High-speed SerDes signal communication faces challenges in maintaining low substrate differential impedance discontinuity from BGA balls to C4 bumps, leading to signal reflections and reduced eye opening, which worsens with increasing data rates beyond 10 Gb/s.
Innovation Solution
The design involves specialized BGA ball assignment, via and PTH placement, metal void and shielding balance, and trace width adjustments, along with a 3D full-wave electromagnetic simulation model to optimize SerDes differential impedance, ensuring variations remain below 10% even at 25 Gb/s data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data rate is increased to 25 Gb/s and beyond, then communication speed is improved, but substrate differential impedance discontinuity increases causing signal reflections
Solution Approach 1:
The patent applies local quality by implementing different structures at different locations along the signal path. Specifically, it uses stacked vias with specific dimensions and spacing arrangements in critical impedance transition zones (at BGA ball, via, PTH, and trace interfaces) to locally optimize impedance matching. The via stack configuration includes controlling via diameter, spacing, and depth to compensate for impedance discontinuities at specific locations, thereby maintaining overall signal quality at 25 Gb/s data rates.
Solution Approach 2:
The patent employs parameter changes by systematically adjusting multiple geometric parameters of the via structure and surrounding features. Key parameters include via diameter, via spacing, via depth, antipad size, and trace width. These parameters are optimized to control the differential impedance along the entire signal path from BGA ball to C4 bump, ensuring impedance variation remains within acceptable limits (less than ±10%) at high data rates.
2Ease of manufacture
If simple methods like enlarging antipad size are used, then manufacturing is simplified, but impedance control becomes insufficient at 25 Gb/s and beyond
Solution Approach 1:
The patent applies segmentation by dividing the via structure into multiple stacked vias rather than using a single via. This segmentation allows independent optimization of each via's dimensions and spacing to control impedance characteristics. The stacked via configuration creates multiple impedance transformation stages, enabling precise control of differential impedance along the signal path while maintaining manufacturability through standard via fabrication processes.
Solution Approach 2:
The patent introduces a vertical dimension by stacking multiple vias along the Z-axis rather than relying solely on planar features like enlarged antipads. This dimensional transition from 2D (antipad size) to 3D (via stack height and configuration) provides additional degrees of freedom for impedance control. The via stack depth and intermediate layer configurations enable precise impedance matching that cannot be achieved with simple planar modifications.
3Reliability
If stacked vias with controlled spacing are implemented, then impedance discontinuity is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the via stack structure. The stacked vias simultaneously provide electrical interconnection between layers, impedance transformation, and signal shielding. By combining these functions into a single integrated via stack configuration, the patent reduces overall device complexity compared to using separate components for each function. The via stack serves as both the interconnection element and the impedance control mechanism.
Solution Approach 2:
The via stack structure is designed to perform multiple functions: it provides vertical electrical interconnection between substrate layers, controls differential impedance through its geometric configuration, and shields signals from external interference. This multi-functionality reduces the need for additional separate components, thereby managing device complexity while achieving superior impedance matching for 25 Gb/s SerDes signals.
Data Source
AI summary
A package design method is disclosed for the optimization of package differential impedance at data rates of 25 Gb/s and beyond. The method optimizes the differential impedance of package vertical interconnections of BGA ball, via, and PTH as well as around the joint between the vertical interconnection and the horizontal interconnection of trace. At 8 ps rise time, a <5% impedance variation is obtained with a 0.8 mm BGA ball pitch and a 10-layer buildup substrate and a <10% impedance variation is obtained with a 1 mm BGA ball pitch and a 14-layer buildup substrate. The method is applicable to all BGA package designs running at 25 Gb/s and beyond.