Package Substrate Impedance Patterns Eliminate Dummy Conductive Layers
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Solution Overview
Problem
Existing fan-out type semiconductor packages face challenges in thickness reduction and warpage control due to the presence of dummy conductive patterns for impedance matching, which restricts the thickness of insulation layers and causes warpage issues.
Innovation Solution
The package substrate design eliminates the dummy conductive pattern by positioning impedance patterns between stacked insulation layers, allowing only the insulation layers to exist between the impedance patterns and redistribution layers, thereby reducing the thickness and controlling warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dummy conductive pattern is arranged between the impedance patterns and the redistribution layers for impedance matching, then the impedance matching is improved, but the thickness of the insulation layer is restricted and cannot be reduced
Solution Approach 1:
The invention extracts and removes the dummy conductive pattern from the structure. By eliminating this unnecessary conductive element, the patent achieves both impedance matching through the optimized insulation layer alone and enables reduction of the insulation layer thickness, resolving the contradiction between reliability and dimensional constraints
Solution Approach 2:
The patent applies parameter changes by adjusting the dielectric constant and thickness of the insulation layer to achieve impedance matching without requiring dummy conductive patterns. This allows the insulation layer thickness to be optimized and reduced while maintaining the required electrical performance
2Reliability
If a dummy conductive pattern is arranged for impedance matching, then the impedance control is improved, but the insulation layer size increases causing warpage control issues
Solution Approach 1:
The invention removes the dummy conductive pattern that was causing the insulation layer to expand in size. By extracting this unnecessary element, the patent reduces the overall insulation layer area while maintaining impedance control through optimized dielectric properties, thereby improving warpage control
Solution Approach 2:
The patent applies local quality by optimizing the dielectric constant and thickness specifically in the regions where impedance control is needed, rather than expanding the overall insulation layer area. This localized optimization maintains electrical performance while minimizing the physical footprint
3Length of moving object
If the insulation layer thickness is reduced to achieve a thinner package substrate, then the overall package thickness is improved, but warpage control becomes more difficult
Solution Approach 1:
The patent applies parameter changes by carefully optimizing the dielectric constant and thickness of the insulation layer. This allows the overall package substrate thickness to be reduced while maintaining adequate warpage control through the optimized electrical and mechanical properties of the insulation layer
Solution Approach 2:
The invention employs composite material strategies by selecting insulation layer materials with specific dielectric constants and mechanical properties that provide both thinness and warpage resistance. The composite structure of multiple insulation layers with different properties enables simultaneous achievement of reduced thickness and improved stability
Data Source
AI summary
A package substrate may include a plurality of stacked insulation layers, a plurality of RDLs and a pair of impedance patterns. The RDLs may be arranged between the insulation layers. The impedance patterns may be arranged on an upper surface of at least one of the insulation layers. The impedance patterns may have an insulation length corresponding to a summed length of thicknesses of at least two insulation layers among the plurality of the insulation layers. Thus, a dummy conductive pattern may not be arranged between the impedance patterns and the RDL so that only the insulation layer may exist between the impedance patterns and the RDL. As a result, the insulation length of the impedance patterns may correspond to the summed length of the thicknesses of the at least two insulation layers.