Package Substrate Impedance Optimization for High-Speed SerDes
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Solution Overview
Problem
High-speed SerDes signal transmission faces challenges with significant substrate impedance discontinuity between BGA balls and C4 bumps, leading to increased differential return loss and degraded signal quality, especially at data rates above 25 Gb/s, where existing methods fail to maintain the desired differential impedance variation within ±10%.
Innovation Solution
The design incorporates specific structural features such as optimized BGA ball assignment, via and PTH placement, metal voids, and trace width adjustments, along with a 3D full-wave electromagnetic simulation model to calculate and adjust parameters like via and PTH spacing, trace lengths, and antipad sizes to achieve less than 10% differential impedance variation for high-speed SerDes signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If simple approaches like increasing antipad diameter are used, then manufacturing is easier, but at 25 Gb/s and beyond, differential impedance variation exceeds ±10% specification
Solution Approach 1:
The patent applies parameter changes by systematically adjusting multiple geometric parameters including antipad diameter, via diameter, via wall thickness, PTH diameter, trace width, and spacing to achieve the desired differential impedance control of ±10% at 25 Gb/s and beyond, moving beyond simple single-parameter adjustments
Solution Approach 2:
The patent transitions from 2D planar adjustments to 3D dimensional control by considering via wall thickness, antipad depth, and multi-layer stacking configurations to achieve precise impedance control that cannot be obtained through simple surface-level modifications
2Speed
If data rate is increased to 25-60 Gb/s for higher speed communication, then transmission speed improves, but substrate impedance discontinuity increases causing signal quality degradation
Solution Approach 1:
The patent uses parameter changes to control impedance discontinuity by adjusting via spacing, antipad dimensions, trace geometry, and PTH configurations to maintain signal integrity at 25-60 Gb/s data rates
Solution Approach 2:
The patent employs iterative optimization using electromagnetic simulation to calculate impedance discontinuity and return loss, then adjusts structural parameters based on simulation feedback until the ±10% impedance variation target is achieved
3Speed
If rise time is reduced for faster signal switching, then data rate increases, but impedance discontinuity is enlarged in the package
Solution Approach 1:
The patent applies parameter changes to compensate for the enlarged impedance discontinuity caused by reduced rise time, adjusting via, PTH, and trace parameters to maintain impedance control despite faster signal edges
Solution Approach 2:
The patent performs preliminary electromagnetic simulation and impedance calculation before finalizing the design, allowing proactive optimization of via and PTH parameters to prevent excessive impedance discontinuity before manufacturing
Data Source
AI summary
Package design method for semiconductor chip package for high speed SerDes signals for optimization of package differential impedance and reduction of package differential insertion loss and differential return loss at data rates of 25 to 60 Gb/s and beyond. The method optimizes parameters of vertical interconnections of BGA ball, via, and PTH, and around the joint between vertical and horizontal interconnections of traces. Also disclosed are examples of chip package designs for high speed SerDes signals, including one using 0.8 mm BGA ball pitch and 10-layer buildup substrate, one using 1 mm BGA ball pitch and 14-layer buildup substrate, one using 6-layer buildup substrate with signals routed on top and bottom metal layers with microstrip line structure, and one using 12-layer package substrate with unique via configuration, all of which achieve low substrate differential impedance discontinuity, reduced differential insertion loss and differential return loss between BGA balls and C4 bumps.