Package Substrate Dedicated Interconnect Layer Signal Uniformity
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Solution Overview
Problem
Existing package substrates face challenges in achieving uniform signal transmission speeds and reducing warping due to variations in signal line widths and thicknesses, which can lead to increased processing times and reliability issues.
Innovation Solution
A package substrate design featuring a dedicated interconnect layer with tailored manufacturing conditions for signal lines, including conductive vias and skip vias, is implemented to reduce variations in signal line widths and thicknesses, with the interconnect layer sandwiched between insulating resin interlayers to enhance signal transmission and prevent warping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional multi-chip module substrates are used with multiple interconnect layers, then electronic components can be connected, but signal transmission speed becomes non-uniform due to variations in signal line widths and thicknesses
Solution Approach 1:
The patent changes the structural parameters of the interconnect system by introducing a dedicated interconnect layer with specific manufacturing conditions that control signal line width and thickness. This dedicated layer uses controlled impedance design and standardized via structures to maintain uniform electrical characteristics across all signal lines, resolving the non-uniform signal transmission speed issue.
Solution Approach 2:
The patent segments the interconnect function by creating a dedicated interconnect layer separate from other functional layers. This segmentation allows independent optimization of signal transmission characteristics in the dedicated layer while other layers handle different functions, thereby achieving uniform signal speeds without compromising overall substrate functionality.
2Reliability
If multiple conductive layers are used to connect electronic components, then connectivity is achieved, but warping occurs due to unbalanced copper distribution
Solution Approach 1:
The patent applies the counterweight principle by strategically distributing copper in the dedicated interconnect layer to balance the overall copper distribution across the substrate. The dedicated layer's copper patterns are designed to counteract warping forces generated by other layers, creating a balanced stress state that prevents substrate deformation while maintaining reliable connections.
Solution Approach 2:
The patent uses local quality by implementing region-specific copper distribution within the dedicated interconnect layer. Different areas of the substrate receive customized copper patterns in the dedicated layer to locally balance stress and prevent warping, while maintaining uniform signal transmission characteristics in each local region.
3Adaptability or versatility
If signal line dimensions vary to accommodate different routing needs, then routing flexibility is improved, but signal transmission speed uniformity deteriorates
Solution Approach 1:
The patent changes the electrical parameters of the dedicated interconnect layer by implementing controlled impedance design. This allows signal lines to have different physical dimensions (width, length) for routing flexibility while maintaining uniform electrical characteristics (impedance, propagation delay) through parameter optimization, thereby achieving both routing adaptability and signal speed uniformity.
Data Source
AI summary
A package substrate includes a core substrate, a first buildup layer and a second buildup layer. The first buildup layer includes an uppermost interlayer, an upper inner interlayer, an uppermost conductive layer including first pads and second pads, an upper first conductive layer, an upper second conductive layer, vias formed through the uppermost interlayer and connecting the upper first conductive layer and the second pads, and skip vias formed through the uppermost and upper inner interlayers and connecting the uppermost and upper second conductive layers. The second buildup layer includes a lowermost interlayer, a lower inner interlayer, a lowermost conductive layer including third pads, a lower first conductive layer, a lower second conductive layer, vias formed through the lowermost interlayer and connecting the lower first conductive layer and third pads, and skip vias formed through the lowermost and lower inner interlayers and connecting the lowermost and lower second conductive layers.