Package Substrate Layout for MUF Void and Misalignment Control
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Solution Overview
Problem
The challenge lies in preventing open circuits and short circuits between semiconductor chips and bump pads, as well as void formation in the mold layer during the molded underfill (MUF) process, which are issues in high-functionality, high-speed, and small electronic components with multi-chip integrated structures.
Innovation Solution
A package substrate design with a substrate base divided into regions, featuring wiring pads and lines of varying horizontal areas, and semiconductor chips with bent shapes, where the wiring pads have different horizontal areas and are arranged to ensure reliable electrical connections and suppress misalignment and deformation during the MUF process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wiring pads have uniform horizontal areas, then manufacturing is simple, but open circuits and short circuits occur between semiconductor chips and bump pads
Solution Approach 1:
The patent applies local quality by dividing the substrate into multiple regions and configuring wiring pads with different horizontal areas according to their specific locations. Wiring pads in first regions have a first horizontal area while wiring pads in second regions have a second horizontal area that is different from the first. This localized differentiation ensures reliable electrical connections in each region without requiring uniform complexity across the entire substrate, thereby resolving the contradiction between connection reliability and structural simplicity.
2Reliability
If wiring pads have different horizontal areas in different regions, then open circuits and short circuits are suppressed, but manufacturing complexity increases
Solution Approach 1:
The patent segments the substrate into multiple regions based on the specific requirements of different areas. By dividing the substrate and assigning different wiring pad configurations to different segments, the patent achieves reliable electrical connections in each region while maintaining a systematic manufacturing approach. The segmentation allows each region to be optimized independently, balancing reliability requirements with manufacturing feasibility.
3Reliability
If semiconductor chips are flat, then chip manufacturing is simple, but misalignment and deformation occur during MUF process
Solution Approach 1:
The patent applies preliminary action by pre-configuring the semiconductor chips with bent shapes before the MUF process. The chips are designed with specific curvature characteristics that anticipate and compensate for deformation forces during molding. This preliminary shaping ensures that chips maintain proper alignment and position during the MUF process, preventing misalignment issues while avoiding the need for complex real-time adjustment mechanisms.
4Reliability
If mold layer is applied uniformly, then manufacturing is simple, but voids form in the mold layer during MUF process
Solution Approach 1:
The patent applies local quality to the molding process by configuring the substrate and chips in a manner that creates optimal local conditions for mold layer application. The varying wiring pad areas and bent chip shapes work together to ensure uniform mold layer coverage in different regions, preventing void formation. This localized optimization allows for reliable mold layer quality without requiring complex molding process adjustments.
Data Source
AI summary
A package substrate includes a substrate base, a plurality of wiring pads, and a plurality of wiring lines. The substrate base includes a first surface and a second surface that is opposite to the first surface. The substrate base is divided into a plurality of regions. The plurality of wiring pads are arranged on the first surface of the substrate base and are apart from each other in a horizontal direction. The plurality of wiring lines are arranged on the first surface of the substrate base and extend from corresponding ones of the plurality of wiring pads, respectively. The plurality of wiring pads have different horizontal area in different regions of the substrate base.