Package Substrate Ball Pattern for Crosstalk-Resistant Dense Pinout

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Solution Overview

Problem

The challenge is to minimize electromagnetic crosstalk between pins on a package substrate while achieving high pin density, which is essential for improving data exchange rates in electronic devices like communications devices and computers, without increasing the package area, thus reducing development costs.

Innovation Solution

The solution involves arranging six first solder balls in a double-parallelogram configuration, with differential and single-ended signal solder balls symmetrically distributed to offset electromagnetic interference, and surrounding them with ground solder balls to form a nonagonal pattern, reducing crosstalk and increasing pin density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If pin arrangement density is increased to reduce package area, then packaging area is reduced, but electromagnetic crosstalk between pins increases

Engineering Contradiction:
Improvepackage areaVSAvoidelectromagnetic crosstalk
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent applies asymmetry by arranging differential signal solder balls and single-ended signal solder balls in non-uniform positions within the unit region. The differential signal solder balls are positioned at specific locations (e.g., at corners or edges of the parallelogram) while single-ended signal solder balls occupy other positions, creating an asymmetric distribution pattern that optimizes electromagnetic interference cancellation while maintaining high density

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The patent uses ground solder balls as intermediary elements surrounding the signal solder balls. These ground balls act as electromagnetic shields or mediators that intercept and dissipate electromagnetic fields, preventing direct crosstalk between adjacent signal pins while allowing the unit regions to remain compact

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If pin arrangement density is increased to improve data exchange rate, then data exchange rate is improved, but electromagnetic crosstalk between pins increases

Engineering Contradiction:
Improvedata exchange rateVSAvoidelectromagnetic crosstalk
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent segments the pin arrangement into distinct functional units: differential signal units, single-ended signal units, and ground reference units. Each type of solder ball is organized into specific sub-regions or patterns within the unit region, allowing independent optimization of each signal type's electromagnetic characteristics while maintaining overall high density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent converts the potentially harmful electromagnetic fields from differential signal solder balls into beneficial interference cancellation effects by strategically positioning single-ended signal solder balls in locations where they experience balanced electromagnetic influence from multiple differential pairs, thereby transforming electromagnetic interference into a shielding mechanism

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS20240014122A1Package Substrate, Semiconductor Device, and Electronic Device
Publication Date: 2024.01.11 HUAWEI TECH CO LTD
  • US20240014122A1 patent drawing
  • US20240014122A1 patent drawing
  • US20240014122A1 patent drawing

AI summary

A package substrate includes a substrate body and a plurality of unit regions disposed on the substrate body. The unit region includes two first solder ball structures. The first solder ball structure includes six first solder balls. The six first solder balls are arranged, with two of them in a row, to form three parallel rows of two solder balls: a first row of solder balls, a second row of solder balls, and a third row of solder balls. Four first solder balls in the first row of solder balls and the second row of solder balls are respectively located at four vertices of one parallelogram, and four first solder balls in the second row of solder balls and the third row of solder balls are respectively located at four vertices of the other parallelogram, and the two parallelograms are arranged axisymmetric about the second row of solder balls.