Semiconductor Package Substrate Layout for Shorter Plating Line Stubs
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Solution Overview
Problem
Conventional semiconductor packaging methods struggle with optimal disposition of plating lines and plating line removal regions, particularly for compact and high-density packages with large semiconductor chips or multiple chips stacked on limited substrates, leading to signal characteristic degradation and adhesion issues.
Innovation Solution
A substrate design with a semiconductor chip mounting region, bonding terminal region, plating line prohibition region, and plating line removal region, where the plating line removal region is strategically placed between the bonding terminal region and the semiconductor chip mounting region to minimize the length of the plating line stub and maintain signal quality, allowing for high integration and compactization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the plating line is extended to connect all terminals for electroplating, then all terminals can be electrically connected and plated, but the plating line stub remaining outside the removal region adversely affects signal characteristics
Solution Approach 1:
The substrate is divided into distinct functional regions: a plating line formation region where plating lines connect terminals for electroplating, and a plating line removal region where plating lines are removed to electrically isolate terminals. This segmentation allows the plating line to serve its electroplating function while preventing signal degradation by removing excess portions.
Solution Approach 2:
The harmful portion of the plating line (the stub outside the removal region) is extracted and removed through etching or other removal processes. This leaves only the necessary plating line portions that connect terminals within the formation region, eliminating the harmful stub while preserving the useful electrical connections.
2Productivity
If the substrate size is increased to accommodate more terminals for higher density integration, then mounting density increases, but the substrate area available for optimal plating line disposition is limited
Solution Approach 1:
Different regions of the substrate are assigned different functions with appropriate qualities: the plating line formation region has high electrical conductivity for electroplating, while the plating line removal region has insulating properties after plating line removal. This local differentiation allows efficient use of substrate area by optimizing each region's characteristics for its specific purpose.
Solution Approach 2:
The plating line removal region is positioned at an opposite side of the bonding terminal region from the semiconductor chip mounting region, utilizing the substrate's dimensional space efficiently. This spatial arrangement allows plating lines to be formed and removed in specific zones without interfering with chip mounting areas, maximizing the usable substrate area for high-density integration.
3Ease of manufacture
If conventional plating line disposition is used for compact packages with large chips, then manufacturing is simpler, but the plating line stub length increases and degrades signal characteristics
Solution Approach 1:
The plating line removal region is predetermined and pre-positioned in the substrate design before the actual plating and removal processes. This preliminary planning ensures that when plating lines are formed and subsequently removed in this predefined region, the resulting stub length is minimized, thereby maintaining signal characteristics while following a straightforward manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the length of the plating line stub, maintaining signal characteristics and enabling high-density layouts while allowing for the mounting of large semiconductor chips on limited substrates, even with multiple chips, without degrading adhesion.
Implementation Method 1
at least one plating line configured to supply electricity for electroplating, that is formed on the one surface of the substrate between the at least one bonding terminal and the semiconductor chip mounting region
Data Source
AI summary
A substrate for a semiconductor package includes a semiconductor chip mounting region; a bonding terminal region including at least one bonding terminal; at least one plating line extending across the semiconductor chip mounting region; a plating line prohibition region at an opposite side of the bonding terminal region from the semiconductor chip mounting region; and a plating line removal region that is between the bonding terminal region and the semiconductor chip mounting region and is free of a portion of the plating line so that each of the at least one bonding terminal is electrically isolated.