Package Substrate Power Ground Pattern Shielding
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Solution Overview
Problem
Semiconductor packages face severe electrical interference between power supply lines, ground lines, and signal lines, leading to signal transmission delays and noise, which existing design schemes have not adequately addressed.
Innovation Solution
A package substrate design featuring power and ground lines on one surface and corresponding lower power and ground patterns on the opposite surface, with the lower patterns positioned to overlap and connect with the upper lines, reducing inductance and resistance while increasing coupling capacitance to minimize interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor packages are made smaller and thinner, then integration density improves, but electrical interference between power supply line, ground line, and signal lines increases
Solution Approach 1:
The patent introduces a third dimension (depth/thickness) for ground and power patterns by creating lower ground and power patterns on the back surface of the substrate. This multi-layer vertical arrangement reduces electrical interference between signal lines while maintaining a compact package footprint, effectively solving the contradiction between small size and reduced interference.
Solution Approach 2:
The lower ground and power patterns act as intermediary shielding layers between signal lines on the front surface and the substrate ground/power layers. These intermediate patterns provide additional electromagnetic shielding and reduce crosstalk, allowing compact packaging without sacrificing electrical performance.
2Ease of manufacture
If conventional single-layer ground and power line designs are used, then manufacturing is simpler, but signal impedance and coupling noises increase
Solution Approach 1:
The ground and power systems are segmented into multiple independent layers: upper ground/power lines on the front surface and lower ground/power patterns on the back surface. This segmentation allows each layer to be optimized independently for its specific function while collectively providing superior electromagnetic shielding and signal integrity compared to a single-layer design.
Solution Approach 2:
The lower ground and power patterns are positioned to overlap with and nest around the projections of upper ground and power lines when viewed from the lateral direction. This nested arrangement creates a multi-layer shielded structure that reduces signal impedance and coupling noises while maintaining manufacturing feasibility through standard PCB lamination processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces signal impedance and coupling noises, enhancing transmission speed and noise removability by shielding electromagnetic fields and optimizing the size of the package substrate.
Implementation Method 1
a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line
Data Source
AI summary
Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided.