Localized High-Density Routing in Package Substrates
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Solution Overview
Problem
Existing multichip package substrates face challenges in achieving high-density routing due to limitations in lithography and plating processes, resulting in lower routing densities and decreased system and power performance.
Innovation Solution
Incorporating a high-density interconnect element with chip-level routing embedded in a substrate medium, allowing for localized high-density routing and bandwidth while using less expensive lithography and plating processes for conventional low-density routing areas, and enabling dimensional variation in placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography and plating processes are used for substrate routing, then manufacturing cost is reduced, but routing density is limited to lower levels
Solution Approach 1:
The patent applies local quality by embedding high-density interconnect elements only in specific localized areas where high routing density is required, rather than applying high-density routing techniques across the entire substrate. This allows expensive high-density interconnect technology to be used only where necessary, while conventional lower-cost processes are used in other areas, thus resolving the contradiction between routing density and manufacturing cost.
Solution Approach 2:
The substrate is segmented into different routing density zones: areas with embedded high-density interconnect elements and areas with conventional routing. This segmentation allows the system to achieve high overall routing density while maintaining cost-effectiveness by using different manufacturing approaches in different regions of the substrate.
2Productivity
If high-density routing is implemented across the entire substrate, then system performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
High-density routing is implemented locally only where performance benefits are most critical, rather than uniformly across the entire substrate. This localized approach maintains system performance while reducing manufacturing complexity and cost by limiting the application of complex high-density interconnect technology to specific high-performance zones.
Solution Approach 2:
The substrate routing is segmented into high-performance zones with embedded interconnect elements and standard zones with conventional routing. This segmentation allows the system to achieve improved overall performance while managing manufacturing complexity by applying different routing densities in different segments.
3Quantity of substance
If uniform routing density is used across the substrate, then manufacturing process is simplified, but bandwidth requirements cannot be met in high-performance areas
Solution Approach 1:
The patent implements local quality by providing high routing density (high bandwidth) in specific localized areas where bandwidth requirements are critical, while using standard routing density in other areas. This resolves the contradiction by matching routing density to actual bandwidth requirements rather than applying uniform routing throughout the substrate.
Solution Approach 2:
The patent adds a vertical dimension to routing density by embedding interconnect elements within the substrate thickness rather than only on surface layers. This three-dimensional approach to routing allows high bandwidth in specific areas without proportionally increasing the horizontal footprint or overall manufacturing complexity.
Data Source
AI summary
Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.