Package Substrate Dummy Region Solder Grounding for ESD Protection

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Solution Overview

Problem

Ball grid array (BGA) semiconductor packages face electrostatic discharge issues during the semiconductor package process, particularly in molding processes, leading to potential operational failures such as short or open circuits due to accumulated static charges.

Innovation Solution

A package substrate design featuring a circuit region surrounded by a dummy region with solders on the bottom surface, where the solders are arranged in a ring-shaped or zigzag pattern and protrude by a controlled height to facilitate electrical connection to a ground terminal, preventing electrostatic discharge by allowing charge dissipation during the mold process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If BGA semiconductor package structure is used to increase input/output terminals and improve electrical performance, then the number of terminals and electrical performance are improved, but electrostatic discharge issues occur during molding process

Engineering Contradiction:
Improvenumber of input/output terminalsVSAvoidelectrostatic discharge resistance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-configuring dummy regions with circuit patterns and solders on the package substrate before the molding process. These dummy regions are specifically designed to provide electrostatic discharge pathways in advance, so when static charges accumulate during the molding process, they can be safely discharged through the pre-established ground connections, preventing electrostatic discharge failures without interfering with the actual circuit operations

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses dummy regions as intermediary elements between the circuit regions and the ground terminal. These dummy regions contain lower circuit patterns connected to ground through solders, acting as a mediator that safely channels electrostatic charges away from the sensitive circuit regions during the molding process, thus protecting the package from electrostatic discharge damage while maintaining the high-density terminal structure

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If dummy region with lower circuit pattern and solders is added to prevent electrostatic discharge, then electrostatic discharge resistance is improved, but device complexity increases

Engineering Contradiction:
Improveelectrostatic discharge resistanceVSAvoidsubstrate structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the electrostatic discharge protection function with the existing substrate structure by integrating dummy regions containing circuit patterns and solders directly into the substrate design. Rather than adding separate protection mechanisms, the dummy regions are combined with the substrate's circuit layout, allowing the same substrate to simultaneously provide electrical connections and electrostatic discharge pathways, thus improving reliability without proportionally increasing device complexity

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The substrate effectively prevents electrostatic discharge failures by ensuring that electric charges can be discharged to the ground, maintaining the integrity of the semiconductor package and reducing the risk of operational failures during fabrication.

Implementation Method 1

solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS10256181B2Package substrates
Publication Date: 2019.04.09 SAMSUNG ELECTRONICS CO LTD
  • US10256181B2 patent drawing
  • US10256181B2 patent drawing
  • US10256181B2 patent drawing

AI summary

A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.