Semiconductor Package Substrate With Stacked Capacitors Against Warpage
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Solution Overview
Problem
Existing semiconductor package structures face challenges with package substrate warpage as they increase in size, due to the limited thickness of core structures when embedding silicon capacitors.
Innovation Solution
The semiconductor package structure incorporates an integrated capacitor structure with stacked capacitors embedded in a core structure, increasing the thickness of the core to reduce warpage and enhance decoupling performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of semiconductor package structure is increased, then the electrical signal performance is improved, but package substrate warpage becomes critical
Solution Approach 1:
The patent transitions from a two-dimensional planar capacitor layout to a three-dimensional stacked capacitor configuration. Multiple capacitor layers are stacked vertically within the core structure, utilizing the vertical dimension to increase capacitance density without expanding the horizontal footprint. This dimensional change allows the package to maintain electrical performance while controlling substrate warpage through optimized thickness distribution.
Solution Approach 2:
The patent embeds multiple capacitor structures nested within each other in a vertical stacking arrangement. Each capacitor layer is positioned within the core structure, with subsequent layers nested above or below previous ones. This nesting approach maximizes the use of available vertical space while maintaining structural integrity and minimizing warpage effects on the package substrate.
2Reliability
If more metal layers are added to meet high electrical signal performance, then electrical signal performance is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple capacitor functions into a single integrated stacked capacitor structure. Instead of implementing separate capacitor components that would require additional metal layers and interconnections, the design merges all capacitor elements into one unified vertical stack, reducing overall device complexity while maintaining electrical signal performance.
Solution Approach 2:
The stacked capacitor structure serves multiple functions simultaneously: it provides decoupling capacitance, acts as an embedded component within the core structure, and contributes to mechanical support. This multi-functionality reduces the need for separate dedicated structures, thereby reducing overall device complexity.
3Reliability
If silicon capacitors are embedded in core structure, then decoupling performance is enhanced, but core structure thickness is limited
Solution Approach 1:
The patent resolves the thickness limitation by transitioning from a single-layer capacitor design to a multi-layer stacked configuration. By stacking capacitors vertically, the design achieves enhanced decoupling performance through increased total capacitance while maintaining a controlled overall thickness. The vertical stacking allows capacitance to scale without proportionally increasing the horizontal dimensions or compromising core structure integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces package substrate warpage and enhances decoupling performance by increasing the core structure thickness through the embedding of stacked capacitors.
Implementation Method 1
an integrated capacitor structure embedded in the core structure
Implementation Method 2
The semiconductor die is disposed over the package substrate and is thermally coupled to the integrated capacitor structure through the redistribution layer
Data Source
AI summary
A semiconductor package structure includes a package substrate and a semiconductor die. The package substrate includes a core structure, an integrated capacitor structure, and a redistribution layer. The integrated capacitor structure is embedded in the core structure. The redistribution layer is disposed over the integrated capacitor structure. The semiconductor die is disposed over the package substrate and is thermally coupled to the integrated capacitor structure through the redistribution layer.