Package Substrate Support Structure Without Pattern Plating
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Solution Overview
Problem
The existing methods for manufacturing package substrates for semiconductor devices are prone to defects due to the complex pattern plating process, which involves multiple steps and is susceptible to resist detachment and contamination, leading to low yield and efficiency.
Innovation Solution
A method using a supporting substrate with a bonding layer and intermediate layers for peeling, allowing for the formation of wiring conductors through etching without pattern plating, thereby simplifying the process and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pattern plating process is used to form wiring conductor, then wiring conductor can be formed, but the process involves many steps and is likely to cause resist detachment and foreign substance contamination
Solution Approach 1:
The patent extracts and removes the pattern plating process from the manufacturing flow, replacing it with a direct etching method. This eliminates the resist attachment and removal steps, chemical polishing steps, and drying steps that are inherent to pattern plating, thereby reducing the total number of process steps while maintaining circuit formation quality.
Solution Approach 2:
Instead of forming the wiring conductor through deposition (plating), the patent uses a subtractive approach where a metal layer is deposited and then etched to form the conductor pattern. This inversion from additive to subtractive manufacturing eliminates the need for resist patterns and reduces process complexity.
2Manufacturing precision
If pattern plating process is used to form wiring conductor, then wiring conductor can be formed, but the process is likely to cause defect in circuit formation
Solution Approach 1:
The patent applies beforehand cushioning by using a carrier foil with a metal layer that is specifically designed to resist detachment during handling and processing. The metal layer is firmly attached to the carrier foil, providing a stable base that prevents defects during the manufacturing process, thereby improving yield.
Solution Approach 2:
The patent converts the potential harm of a complex multi-step process into a benefit by simplifying the process to fewer steps. The direct etching method, while simpler, maintains circuit formation quality and reduces the opportunity for defects to occur during resist attachment, exposure, development, and removal steps.
3Manufacturing precision
If pattern plating process is used to form wiring conductor, then wiring conductor can be formed, but the process requires many steps including chemical polishing, resist attachment, exposure, development, drying, water washing, acid washing, electroplating, drying, resist peeling and drying
Solution Approach 1:
The patent merges multiple separate process steps into a simplified flow. Instead of treating resist attachment, exposure, development, etching, and resist removal as separate sequential steps, the direct etching method combines these functions into a more streamlined process that achieves the same circuit formation goal with fewer discrete operations.
Solution Approach 2:
The patent skips the resist-related steps (attachment, exposure, development, peeling) and drying steps by using a direct etching method. This allows the manufacturing process to rush through to the essential circuit formation step without being delayed by intermediate resist processing operations, thereby improving production efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances production efficiency and yield by eliminating the need for pattern plating, ensuring reliable circuit formation and easy separation of layers, resulting in a high-quality package substrate for semiconductor devices.
Implementation Method 1
forming a first wiring conductor in the first laminate by etching the first metal layer
Implementation Method 2
subjecting the insulating resin layer with the non-through hole formed therein to electrolytic plating and/or electroless plating
Implementation Method 3
subjecting the insulating resin layer with the non-through hole formed therein to electrolytic plating and/or electroless plating
Data Source
Figure 1
Figure 2(A)~2(G)
Figure 3(A)~3(G)
AI summary
A method for manufacturing a package substrate for mounting a semiconductor device including: a first laminate preparing step of preparing a first laminate including a resin layer, a bonding layer that is provided on at least one surface side of the resin layer and includes peeling means, and a first metal layer provided on the bonding layer; a first wiring forming step of forming a first wiring conductor in the first laminate by etching the first metal layer; a second laminate forming step of forming a second laminate by laminating an insulating resin layer and a second metal layer in this order on a surface of the first laminate, the surface being provided with the first wiring conductor; a second wiring forming step of forming a second wiring conductor on the insulating resin layer by forming a non-through hole in the insulating resin layer, the non-through hole extending to the first wiring conductor, and subjecting the insulating resin layer with the non-through hole formed therein to electrolytic plating and/or electroless plating; and a peeling step of peeling at least the resin layer off from the second laminate with the second wiring conductor formed therein.