Package Substrate Third Wiring Layer for Pad Non-Wetting
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Solution Overview
Problem
The existing package substrates for flip-chip type semiconductor packages face limitations in increasing electrical connections due to limited space for conductive pads, leading to poor bonding strength and non-wetting issues between pads and solder materials, which reduces product reliability and yield.
Innovation Solution
A package substrate design featuring an insulating layer with first and second wiring layers, conductive vias, and metal bumps formed on the conductive pads, where the metal bumps' projected area is less than the pad area, enhancing bonding strength and preventing non-wetting problems during solder material bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of electrical connections is increased to meet chip functionality requirements, then the connectivity is improved, but the available area for conductive pads is reduced, leading to poor bonding strength and non-wetting problems
Solution Approach 1:
The patent introduces a third wiring layer formed on the first surface of the insulating layer, adding a vertical dimension to the wiring structure. This third layer provides additional conductive paths without consuming lateral pad area, enabling increased electrical connections while maintaining adequate pad bonding area. The third wiring layer is electrically connected to the first wiring layer through conductive vias, creating a three-dimensional wiring architecture that resolves the area constraint.
2Productivity
If the conductive pad area is reduced to accommodate more connections, then the connection density is improved, but the bonding strength between pads and solder materials deteriorates
Solution Approach 1:
By forming a third wiring layer on the first surface and connecting it to the first wiring layer via conductive vias, the patent creates additional connection pathways in the vertical dimension. This allows the first conductive pads to maintain their original area and bonding strength while the third wiring layer provides additional connection points, effectively increasing connection density without compromising bonding strength.
Solution Approach 2:
The patent segments the wiring function across three separate wiring layers instead of concentrating all connections in a single plane. The first wiring layer embeds in the insulating layer, the third wiring layer forms on the first surface, and conductive vias provide vertical interconnection. This segmentation distributes the connection load across multiple layers, allowing each pad to maintain adequate bonding area while achieving higher overall connection density.
3Adaptability or versatility
If the conductive pad area is reduced, then more connections can be made, but non-wetting problems occur between solder materials and pads
Solution Approach 1:
The third wiring layer formed on the first surface provides additional connection interfaces that do not compete with the first conductive pads for lateral area. This vertical expansion of the wiring structure enables more connections to be made while the original pads maintain their full area, ensuring proper wetting quality between solder materials and pads is preserved.
Data Source
AI summary
A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.