Package Substrate Fabrication Using Vertical Conductive Stacking

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Solution Overview

Problem

Current IC package substrate technologies face challenges in achieving high-density, miniature designs with thick circuit wires, as existing fine-pitch processes like SAP limit wire thickness to 20 μm, making it difficult to thicken wires in fine-pitch circuitry for high-power electronic products.

Innovation Solution

A method involving multiple dielectric and conducting layers is used, where conducting units with heights greater than dielectric layer thickness and widths greater than opening widths are formed, allowing for thicker wires by filling openings and removing carriers and dielectric layers to create a package substrate with reduced resistivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If fine-pitch process (SAP) is used to reduce package lead pitch, then line width and line pitch can be reduced to 15-20 μm, but circuit wire thickness is limited to 20 μm at most

Engineering Contradiction:
Improveline pitchVSAvoidwire thickness
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent transitions from planar wire formation to three-dimensional wire formation by building wires vertically through multiple dielectric layers. Conductive units are formed in different layers (first, second, third dielectric layers) and connected vertically, enabling wire thickness to exceed the limitations of single-layer SAP processes while maintaining fine pitch dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the wire formation process into multiple segments across different dielectric layers. Instead of forming a single thick wire in one layer, the wire is segmented into multiple conductive units stacked vertically, each formed within the capabilities of standard SAP processes, then interconnected to achieve the desired thick-wire structure.

Inventive Principle:
Principle #1Segmentation

2Reliability

If thick circuit wire is formed to reduce resistivity for high power products, then resistivity decreases, but it becomes comparatively difficult to thicken wires in fine-pitch circuitry design

Engineering Contradiction:
ImproveresistivityVSAvoidwire thickening process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent resolves the complexity of thickening wires in fine-pitch designs by moving from horizontal thickening to vertical thickening. Multiple conductive units are stacked in the vertical dimension across different dielectric layers, achieving reduced resistivity through increased wire cross-sectional area without requiring complex horizontal wire thickening processes that would compromise fine-pitch dimensions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Manufacturing precision

If multiple dielectric and conducting layers are stacked to form thick wires, then wire thickness increases and resistivity decreases, but process complexity increases

Engineering Contradiction:
Improvewire thicknessVSAvoidmulti-layer process
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the wire formation into multiple manageable layers, with each layer processed through standard SAP techniques. The first, second, and third dielectric layers are processed separately with their respective conductive units formed independently, then interconnected. This segmentation allows each layer to be manufactured with conventional precision while achieving cumulative thick-wire structures.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10745818B2Method of fabricating package substrates
Publication Date: 2020.08.18 PHOENIX PIONEER TECH
  • US10745818B2 patent drawing
  • US10745818B2 patent drawing
  • US10745818B2 patent drawing

AI summary

This disclosure provides a package substrate fabrication method including: providing a carrier; forming a first dielectric layer on the carrier while enabling the first dielectric layer to be patterned including an opening; forming a first conducting unit on the carrier while enabling the first conducting unit to fill up the opening, a height of the first conducting unit at the opening larger than a thickness of the first dielectric layer, and a width of the first conducting unit larger than a width of the opening; forming a second dielectric layer on the first conducting unit; forming a second conducting unit on the second dielectric layer; forming a third dielectric layer on the second conducting unit; removing the carrier and the first dielectric layer while enabling the part of the first conducting unit in the opening to be removed; and forming a fourth dielectric layer to cover the first conducting unit.