Semiconductor Package Substrate With Vertical Thermoelectric Heat Path

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Solution Overview

Problem

Current semiconductor packaging technologies face challenges in achieving high heat-dissipation efficiency and compact size, especially for portable electronic devices, where the integration of multiple components into a single package is necessary.

Innovation Solution

The semiconductor package incorporates a package substrate with an insulating portion that includes interconnection patterns and a heat-dissipation pattern. The heat-dissipation pattern consists of alternately stacked conductive and thermoelectric patterns, utilizing n-type semiconductor material, to efficiently transfer heat and electrical power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If multiple semiconductor chips are integrated into a single package to reduce size, then the compactness is improved, but the heat-dissipation efficiency deteriorates

Engineering Contradiction:
Improvepackage sizeVSAvoidheat-dissipation efficiency
Core Design Contradiction:
Volume of moving objectVSTemperature

Solution Approach 1:

The patent transitions from planar heat dissipation to three-dimensional heat dissipation by stacking thermoelectric patterns vertically through multiple insulating portions. This vertical arrangement enables heat to be dissipated in the depth dimension rather than only in the planar direction, effectively managing heat in compact packages.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs composite material structures by combining conductive patterns (for electrical connection) with thermoelectric patterns (for heat dissipation) within the same interconnection system. This composite approach allows simultaneous achievement of electrical functionality and thermal management in a integrated manner.

Inventive Principle:
Principle #40Composite materials

2Temperature

If thermoelectric patterns are added to improve heat dissipation, then the heat-dissipation efficiency is improved, but the device complexity increases

Engineering Contradiction:
Improveheat-dissipation efficiencyVSAvoidstructure complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent achieves multi-functionality by designing the heat-dissipation pattern to simultaneously provide electrical connection (through conductive patterns) and thermal management (through thermoelectric patterns). This universal design eliminates the need for separate heat dissipation structures, thereby reducing overall device complexity while maintaining effective heat dissipation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the electrical interconnection function and thermal management function into a single integrated pattern system. The conductive and thermoelectric patterns are combined within the same structural framework, allowing both functions to be achieved without adding separate complex subsystems.

Inventive Principle:
Principle #5Merging (Combining)

3Device complexity

If conventional interconnection patterns are used for both signal and power, then the device complexity is reduced, but the electrical characteristics deteriorate

Engineering Contradiction:
Improveinterconnection structureVSAvoidelectrical characteristics
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies local quality differentiation by providing distinct interconnection patterns for different functions: conductive patterns for signal transmission and thermoelectric patterns for power delivery and heat dissipation. This localized functional differentiation optimizes electrical characteristics for each specific requirement while maintaining overall structural simplicity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration enhances both the electrical characteristics and heat-dissipation efficiency of the semiconductor package, allowing for reduced size and weight while effectively managing heat generated by semiconductor chips.

Implementation Method 1

a heat-dissipation pattern provided in the insulating portion to electrically connect the semiconductor chip to the at least one power terminal. The heat-dissipation pattern may include at least one conductive pattern and at least one thermoelectric pattern, connected in series

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Implementation Method 2

The thermoelectric device has been receiving a lot of attention due to recent clean energy-oriented policies. In the 1800s, the thermoelectric effect was discovered by Thomas Johann Seebeck.

Methodology Applied
Scientific EffectThermoelectric effect: Peltier Effect

Data Source

PatentUS20250029885A1Semiconductor package and methods of forming the same
Publication Date: 2025.01.23 SAMSUNG ELECTRONICS CO LTD
  • US20250029885A1 patent drawing
  • US20250029885A1 patent drawing
  • US20250029885A1 patent drawing

AI summary

A semiconductor package may include a package substrate, a semiconductor chip on the package substrate, and one or more outer terminals below the package substrate. The one or more outer terminals may include at least one signal terminal delivering an operation signal to the semiconductor chip and at least one power terminal supplying an electric power to the semiconductor chip. The package substrate may include an insulating portion, one or more interconnection patterns provided in the insulating portion to electrically connect the semiconductor chip to the at least one signal terminal, and a heat-dissipation pattern provided in the insulating portion to electrically connect the semiconductor chip to the at least one power terminal. The heat-dissipation pattern may include at least one conductive pattern and at least one thermoelectric pattern, which are connected in series in a direction from the one or more outer terminals toward the semiconductor chip.