Package Substrate Via Structure for Impedance and Inductance Control
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Solution Overview
Problem
Impedance mismatch and high inductance in through-hole vias of package substrates lead to signal integrity and electrical performance issues, particularly in high-speed applications.
Innovation Solution
A package substrate design that eliminates through-hole vias, utilizing a dielectric layer structure with metal pillars and vias that decrease in diameter from one layer to another, along with a metal interconnect structure to maintain consistent impedance and reduce inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-hole vias are used in package substrates, then vertical connections between layers are enabled, but impedance mismatch and high inductance occur leading to signal integrity issues
Solution Approach 1:
The patent segments the via structure into multiple components: a via hole through the dielectric layer, a conductive filler material within the via, and a metal cap structure covering the via opening. This segmentation allows each component to address specific issues - the via hole provides the vertical connection path, the conductive filler provides electrical conductivity, and the metal cap reduces inductance and prevents impedance mismatch by providing a continuous conductive surface.
Solution Approach 2:
The patent transitions from traditional planar via structures to a three-dimensional via-with-cap structure. The metal cap adds a horizontal dimension to the via, creating a via-in-pad structure that extends beyond the simple vertical hole. This dimensional change allows the via to maintain consistent impedance by providing a larger effective conductive area and reducing the inductive loop area.
2Ease of manufacture
If traditional via structures are used, then manufacturing simplicity is maintained, but electrical performance deteriorates in high-speed applications
Solution Approach 1:
The patent applies preliminary action by forming the metal cap structure over the via holes before completing the final dielectric layer processing. The cap structures are formed in advance to establish the desired electrical characteristics and impedance control, and then subsequent processing steps are performed around these pre-formed caps. This preliminary formation of the cap structure ensures that the electrical performance requirements are met before final assembly.
3Ease of manufacture
If via diameter remains constant through layers, then manufacturing is easier, but impedance consistency and inductance control are compromised
Solution Approach 1:
The patent applies local quality by varying the via structure at different locations and depths. The via holes may have different diameters at different depths, and the metal caps have different sizes and shapes tailored to specific via locations. This localized customization allows each via to be optimized for its specific electrical requirements while maintaining overall manufacturing feasibility through standardized processes.
Data Source
AI summary
A package substrate includes a dielectric layer structure including a first dielectric layer and a second dielectric layer, a plurality of bonding pads located at a lower surface of the first dielectric layer, a plurality of metal pillars located on an upper surface of the second dielectric layer, and a metal interconnect structure extending from the plurality of bonding pads to the plurality of metal pillars and including a plurality of first metal vias in the first dielectric layer and a plurality of second metal vias in the second dielectric layer, wherein the plurality of first metal vias and the plurality of second metal vias have a cross-sectional diameter that decreases in a direction from the second dielectric layer to the first dielectric layer.