Package Substrate Vias with Resin-Filled Holes for CAF Prevention
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Solution Overview
Problem
Current package substrates for high reliability systems, such as Advanced Driver Assistance Systems (ADAS), face challenges with conductive anodic filament (CAF) failures, leading to reliability issues and constraints on feature sizes, particularly in via pitches, which existing materials like glass-cloth dielectrics and prepreg materials fail to adequately address.
Innovation Solution
A package substrate architecture and process flow that involves drilling a larger hole in a glass-cloth material, filling it with a conventional build-up resin, and then drilling a smaller via within, ensuring the Cu-plated via is surrounded by resin to prevent CAF failures, allowing for tighter via-via pitches down to approximately 107 um, while using existing tools and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If glass-cloth dielectrics are used in package substrates, then manufacturing capability is improved, but conductive anodic filament (CAF) failures occur leading to reduced reliability
Solution Approach 1:
The package substrate is divided into multiple layers: a core layer containing glass-cloth dielectric material, and at least one build-up layer formed above it. This segmentation allows the glass-cloth core to provide manufacturing advantages while the build-up layers provide CAF protection, resolving the contradiction between ease of manufacture and reliability.
Solution Approach 2:
The patent uses a composite structure combining glass-cloth dielectric material in the core layer with additional build-up dielectric layers. This composite approach leverages the manufacturing benefits of glass-cloth while adding protective layers that prevent CAF failures, thus improving reliability without sacrificing ease of manufacture.
2Productivity
If via pitches are reduced to increase density, then productivity is improved, but CAF failures increase due to closer spacing
Solution Approach 1:
The patent addresses the via pitch limitation by adding a vertical dimension to the protection scheme. Instead of only increasing lateral spacing, build-up layers are added above the core layer to provide CAF protection. This allows reduced via pitches for higher density while maintaining reliability through the vertical protective barrier.
3Reliability
If larger via holes are drilled to reduce CAF failures, then reliability is improved, but manufacturing precision is worsened due to larger feature sizes
Solution Approach 1:
The via structure is segmented into the core layer via (which can be smaller) and the protective build-up layers. This segmentation allows the core via to be optimized for electrical function while the build-up layers provide the CAF protection that would otherwise require larger via holes, thus maintaining manufacturing precision while improving reliability.
Data Source
AI summary
Embodiments herein describe techniques for a semiconductor device including a package substrate. The package substrate includes a via pad at least partially in a core layer. A first dielectric layer having a first dielectric material is above the via pad and the core layer, where the first dielectric layer has a first through hole that is through the first dielectric layer to reach the via pad. A second dielectric layer having a second dielectric material is at least partially filling the first through hole, where the second dielectric layer has a second through hole that is through the second dielectric layer to reach the via pad. A via is further within the second through hole of the second dielectric layer, surrounded by the second dielectric material, and in contact with the via pad. Other embodiments may be described and/or claimed.