Package Substrate Stress-Relief Holes for Reflow Warpage
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Solution Overview
Problem
Semiconductor packaging substrates often warp during high-temperature reflow procedures due to mismatched coefficients of thermal expansion (CTEs) and residual stresses, leading to contact issues like non-wet defects.
Innovation Solution
The introduction of stress relief through holes in the package substrate, which penetrate the base substrate and solder resist layers, helps to release residual stresses and reduce warpage. These holes can be filled with materials having high modulus and low CTE to further mitigate warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple layers with different materials are used to form the package substrate, then the functional requirements are met, but warpage occurs due to mismatched coefficients of thermal expansion
Solution Approach 1:
The patent introduces stress relief through holes that change the physical parameters of the substrate by creating pathways for stress redistribution. This structural modification allows the substrate to accommodate thermal expansion differences without warping, directly addressing the contradiction between functional material diversity and shape stability
Solution Approach 2:
The substrate is segmented into multiple layers with through holes penetrating through them. This segmentation allows independent stress management in each layer while maintaining overall structural integrity, preventing warpage caused by CTE mismatch between different functional layers
2Productivity
If the package substrate includes a plurality of unit substrates, then the packaging capacity is increased, but the warping effect accumulates across the entire substrate
Solution Approach 1:
The package substrate is divided into multiple unit substrates arranged in a matrix, with stress relief through holes positioned between adjacent units. This segmentation isolates warpage effects to individual units while maintaining overall package integrity, preventing cumulative warpage across the entire substrate
Solution Approach 2:
Stress relief through holes are positioned at the boundaries between unit substrates to act as intermediaries that absorb and distribute stress. These through holes serve as stress break points that prevent warpage accumulation from propagating across adjacent unit substrates
3Volume of moving object
If the package substrate is made thin to reduce size, then the compactness is improved, but the substrate becomes more prone to warpage
Solution Approach 1:
The introduction of through holes changes the structural parameters of the thin substrate, creating a three-dimensional stress distribution pattern that compensates for the reduced thickness. This parameter change allows the thin substrate to maintain dimensional stability despite its reduced size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of stress relief through holes significantly reduces warpage in semiconductor packaging substrates, improving package quality by preventing contact defects and enhancing the mismatch of CTEs between materials.
Implementation Method 1
a plurality of stress relief through holes penetrating the base substrate, the first solder resist layer and the second solder resist layer
Implementation Method 2
a stress relief through hole of the plurality of stress relief through holes may be disposed on a side of each unit substrate of the plurality of unit substrates... the plurality of stress relief through holes may be at least partially filled with a filler comprising a material having a high modulus and a low coefficient of thermal expansion
Data Source
AI summary
A package substrate includes: a base substrate; a first conductive layer disposed on a first surface of the base substrate; a second conductive layer disposed on a second surface of the base substrate opposite the first surface of the base substrate; a first solder resist layer disposed on the first surface of the base substrate; a second solder resist layer disposed on the second surface of the base substrate; a plurality of contact plugs penetrating the base substrate and electrically connecting the first and second conductive layers; and a plurality of stress relief through holes penetrating the base substrate, the first solder resist layer and the second solder resist layer.